A Really Solderless Breadboard — Part 1
8, 16, 27, 42, 49, 60
38, 73, 78
JTAG control signal
Table 1. CPLD Connections for XC9572 or XC95108
in PLCC84 package
specific time delays and other real world factors into
account. Again, if the behavior is not what you expect, go
back to Step 1.
6. Use JTAG programming software to burn the chip (this
can be done while the chip is in the final circuit, if
desired). Since you've simulated the device, it should
work perfectly. Of course, real world problems can get in
the way of this ideal goal, but, overall, it usually works out
The software simulation is especially powerful. For
learning purposes, you don't even need any hardware.
Just download the free software, design circuits, and
examine their behavior using simulation. It's educational
and you can't beat the price!
The first step in any PLD design is to capture what
you want the device to do using schematics or an HDL.
This step is known as design entry. Unless your project is
trivial, you'll probably want to partition your design into
several modules. For example, if you were going to build
a digital clock on a chip, you might plan on having a
module that counts in BCD and another that decodes
BCD digits to drive a seven segment LED. Another
module might generate a time base.
Partitioning has several advantages. First, you can
simulate each piece separately and work out the bugs
before you try to join all the pieces together. Second,
Figure 4. The half adder circuit adds two binary digits,
producing a digit and a carry.
NUTS & VOLTS
small functional blocks are often usable in multiple
projects. Finally, you can mix and match tools to suit your
needs. For example, writing a BCD decoder in Verilog is
very simple. Drawing it in a schematic form is very
complex. So, you might use Verilog to write the BCD digit
decoder, but then use a schematic to show how the digit
decoders connect to the BCD counter (the counter might
also be a Verilog module).
No matter what method you use to handle design
entry, you'll want to do a quick check of the finished
product before you proceed. If you use a hardware
definition language, this will check basic syntax. For the
schematic editor, the check will look for nodes that are
not connected and other obvious mistakes.
The WebPack has several ways you can perform
simulation. After design entry, you'll want to use the
TestBencher tool to create example input wave forms.
Then, you can have WebPack generate the expected
output waveforms automatically. At this stage, you'll only
be looking for logic mistakes. After you've fixed all of the
errors you find, you'll be ready to go on to the fitting step.
Obviously, to perform the fitting step, you'll need to
have a device in mind. If your design won't fit, you'll have
to modify your design or select a larger device. Another
consideration during fitting is the floor plan of the chip.
Normally, the first time you fit the chip, the fitter software
will select which external pins connect to which signals.
However, in some cases, you may want to select pin
associations yourself. For example, if you already have a
printed circuit board layout, you'll want to force the pins
to the proper locations. Before fitting, you can use a
special editor to associate signals with pins.
If fitting works without any problems, you'll want to
do a post fit simulation and analysis. This serves two
purposes. First, it performs a simulation that accounts for
propagation delays in the actual chip. Second, it enables
you to perform timing analyses to determine things like
the maximum clock speed the chip can accept.
Once everything is working, you'll use the
programming software to download the configuration into
the chip. One nice thing about the CPLDs we'll use is that
they hold their own configuration and are electrically
erasable. Some larger FPGAs require external memory
devices (like EEPROMs) that reconfigure the device every
time you apply power. That's generally not the case with
the CPLD devices.
All that's left is hardware. Nearly all of the CPLD's
pins are for I/O. Table 1 shows the connections you need
to make. Notice that there are two separate groups of
power pins. One set connects to the core voltage and the
other connects to the I/O pin voltage. It is possible to
operate at different voltage levels (for example, 3. 3 V), but
in these examples, I'll use 5 V throughout the system.
So, all you really need are the connections to power
and ground. In addition, the four JTAG pins ( 28, 29, 30,
and 59) require connections to the programmer for