configuration. For some designs, you may want to
take advantage of certain specialized pins on the IC. For
example, there are several global clock inputs. You can
use these pins as ordinary inputs or outputs. However, if
you assign a synchronous clock input to the pin, special
routing circuitry inside the chip can improve the clock
skew performance (compared to using ordinary pins for
An Adder Design
A half adder (Figure 4) is a classic logic circuit. It
accepts two inputs and produces a binary sum and a
carry; a full adder takes two bits plus a carry from the
previous adder. As you can see, the circuit is fairly simple,
but you'd need a couple of ICs to wire it up by hand.
To start this design, run WebPack. This brings up the
Project Manager. You'll need to make a new project by
selecting File | New Project from the menu. You'll see the
dialog box in Figure 5. The project name is hadd. In the
example, I'll use an XC95108 device, although you could
select XC9572 if that's the chip you are using. Both
devices are much larger than this simple circuit and will
work equally well.
I won't use Verilog in this project, but, as a matter of
habit, I picked XST Verilog in the design flow box. You
could also pick VHDL or EDIF; EDIF is a common format
that many third-party tools produce.
Once you've created the new project, you'll see an
Explorer-style window to the left of the screen. If you right-click on the hadd entry, you'll see a menu. Select New
Source from this menu. This will bring up a dialog that lets
you add a new document to the project. You can create a
Verilog module, a state diagram, or a schematic. In
this case, we'll create a schematic named hadd.
Once you've created the schematic, you'll save
it and use the Tools | Check Schematic menu item
to check for obvious mistakes. You can find
detailed instructions for using the schematic editor
in the online help site (see Resources). Here are a
few common pitfalls:
Figure 5. The new project dialog box.
names. You can also name a node by selecting Add | Net
Name from the main menu.
If you want to test your half adder, add another source
to your project. This time, select Test Bench Waveform as
the document type. I called my document haddtest. Don't
use the same name as the schematic; this can cause
problems later down the road. You will want to associate
the Test Bench with hadd, of course.
The Test Bencher software will ask you to set up a clock
(Figure 6). Since the adder doesn't require a clock — it is a
combinatorial design — you can ignore the clock setup and
just accept the default delays for the combinatorial setup.
After you complete the setup, you can view the input
and output waveforms. Of course, you'll want to edit the
input waveforms. You can click on the waveform to toggle
its value from the mouse cursor forward. You can also use
the menu commands to insert clocks or counting values
Figure 6. Setting up a new test bench.
• The input and output markers must touch a wire.
You can't place a component and then drop a
marker on top of the component. You must draw a
small wire stub first.
• If you make a mistake and need to select wires
for moving or deleting, pay attention to the toolbar
near the top of the screen. If you pick Select
Branches, you'll select a wire and everything connected to it. If you pick Select Wire, you'll be able
to pick just a specific line segment out of the total
• Double click the I/O markers to change the node