U N D E R S T A N D I N G Digital Logic ICs
early 1980s, advances in CMOS
fabrication techniques yielded speed
performances similar to LS TTL,
but with CMOS levels of power
consumption. HC 74-series devices
using this technology have CMOS-compatible inputs. Typically, a single
74HC00 two-input NAND gate consumes less than 1µA of quiescent current,
and has a propagation delay of 8 nS.
High-Speed (HCT) CMOS — These are
HC-type devices, but have TTL compatible inputs. Typically, a 74HCT00
two-input NAND gate consumes less
than 1µA of quiescent current and has
a propagation delay of 18 nS.
Advanced High-Speed (AC) CMOS —
In the late 1980s, advances in CMOS
design and further advances in CMOS
fabrication techniques yielded speed
performance similar to those of ALS.
AC 74-series devices using this technology have CMOS-compatible inputs.
Typically, a 74AC00 two-input NAND
gate has a propagation delay of 5 nS.
Advanced High-Speed (ACT) CMOS
— These are AC-type devices, but
have TTL-compatible inputs. Typically,
a 74ACT00 two-input NAND gate
has a propagation delay of 7 nS.
Family is Best?
Two major general-purpose logic
families are currently available: the
4000-series low-speed CMOS family
and the high-speed 74-series TTL/
CMOS family (a third family, using ECL
technology, is very specialized and
intended for use in very high-speed
applications). The 4000-series (which
will be described in Part 4) is of particular value in circuits operating below
frequencies of a few MHz in which a
minimal figure of quiescent current
consumption is desired. Other major
advantages of the series are that its ICs
can operate from any supply in the 3 to
15 V range, have excellent noise immunity, and have ultra-high input impedances.
The 74-series is of special value in
circuits operating at frequencies up to
several tens of MHz, in which low
56 August 2006
quiescent current consumption is not
too important and in which the ICs can
be powered from a well-regulated DC
supply (typically of + 5 V). If you decide
to use a 74-series IC, you are faced
with the problem of deciding “which
sub-family is best for my application?”
Sub-Family is Best?
When designing a new logic
circuit, ICs should always be selected
on a basis of commercial (rather than
purely technical) superiority. It would,
for example, be foolish to use a really
fast ALS gate in an application in which
a slower LS or HC device would be
perfectly adequate and was readily
available at a fraction of the cost of the
ALS device. With this point in mind,
note that the five 74-series IC sub-families most widely available at the
time of writing are Standard and LS TTL,
and HC, HC T and AC CMOS. Of these,
Standard TTL is technically and
commercially inferior to LS and is not
recommended for use in new designs.
The AC CMOS cost approximately 2.5
times as much as LS TTL or HC/HCT
CMOS and should thus only be used in
special applications. HC T is only meant
to be used as a replacement for TTL
devices in existing designs and should
not really be used in new designs. That
leaves just LS TTL and HC CMOS.
Of these two 74-series sub-families,
LS is slightly faster than HC and is available in a far greater range of functional
device types, but generally consumes
more supply current/power than HC at
frequencies below about 5 MHz.
(Figure 12 compares the performances
of 74LS00 and 74HC00 gates.) Thus, for
most new design applications, the LS
TTL and HC CMOS sub-families
deserve a joint ‘best’ award, with a
slight edge perhaps going to LS.
TTL Logic Levels and
All digital ICs handle input and
output signals that switch between the
high (logic-1) or low (logic-0) states. In
TTL, each of these logic levels must fall
within a defined range of voltage lim-
its. Figure 13 shows the typical input-to-output voltage curve of a Standard
T TL inverter that operates from a + 5 V
supply and has a lightly loaded output.
Note that the output is high, at + 3. 5 V,
until the input rises to 0.7 V, and then
falls fairly linearly as the input is further
increased, and eventually stabilizes at
a low value of about 0.25 V when the
input rises above 1.5 V.
In practice, all Standard and LS
TTL ICs are — when using a + 5 V
supply — guaranteed to recognize
any input voltage of up to 0.8 V as
being a logic-0 input, and of 2.0 V or
above as being a logic-1 input. Note
that the area between these two levels is known as the IC’s indeterminate
zone or region, and operation within
this zone should be avoided.
In TTL circuitry, different logic levels are used to define input and output
signals, since TTL output voltage levels
vary considerably with loading conditions. Figure 14 shows how — when an
input of 0.4 V is applied to the above
TTL inverter — the logic-1 output
voltage falls from + 3. 5 V at near-zero
load current, to a mere 2.0 V at a load
current of 13 mA, and so on. In
practice, all Standard TTL ICs are guaranteed (when using a + 5 V supply) to
recognize any output voltage of up to
0.4 V as being a logic-0 output, and of
2.4 V or above as being a logic-1
output. On LS TTL ICs, these levels are
0.5 V for logic-0, and 2.7 V for logic-1.
When one TTL output is connected
directly to a following TTL input, any
excessive noise on the output signal
may cause incorrect operation of the
following input stage. Thus, taking a
worst-case situation, a logic-1 Standard
TTL output may be as low as 2.4 V, and
any superimposed negative-going noise
pulse greater than 0.4 V will drive the
following input below the 2.0 V ‘logic-0’
defined threshold and may cause it to
erroneously recognize its input as being
a logic-0 (rather than logic-1) signal.
The maximum worst-case magnitude of noise that a digital IC can ignore
under these conditions is known as its
noise immunity or noise margin value,
and equals the difference between the
logic-0 or logic-1 output/input threshold
values. With Standard TTL, noise