THE DESIGN CYCLE
24 system clock cycles to execute.
The Silicon Laboratories’ CIP- 51 core
executes 70% of its instructions in one
or two system clock cycles, with only
four of 190 instructions taking more
than four system clock cycles. The old
8751 could only crank up 0.5 MIPS
with a 12 MHz clock. The Silicon
Laboratories’ CIP- 51 core can peak
at 100 MIPS when powered by its
PLL-assisted 100 MHz clock.
There are plenty of C8051F120
on-chip gadgets we can put to work in
an application. However, if we don’t
have our arms around the C8051F120
basics, we won’t even be able to blink
an LED. So, let’s examine the
C8051F120’s basic subsystems.
The Silicon Laboratories
C8051F120 devices include an on-chip 8KB RAM block and an external
memory interface (EMIF) for accessing
off-chip data memory. Using overlapping 8KB boundaries, the on-chip 8KB
RAM block can be addressed over the
entire 64KB external data memory
address range. External data memory
address space can be mapped to allow
the programmer to use only the
on-chip memory or a combination of
on-chip and external memory.
For instance, addresses up to the
8KB boundary can be directed to on-chip memory and any addresses
above the 8KB address marker are
directed to EMIF. If you’re using
external memory that multiplexes the
address and data lines, the EMIF
can be configured to accommodate
multiplexed address/data lines. Figure
3 is a graphical depiction of the
C8051F120’s external RAM space.
The C8051F120’s program memory consists of 128KB of banked Flash
memory. As you can see in Figure 4,
the 1024 bytes between addresses
0x1FC00 and 0x1FFFF are reserved.
This memory may be reprogrammed
in-system in 1024 byte sectors, and
requires no special off-chip programming voltage. Notice that there are
also two 128-byte sectors beginning at
address 0x20000 and ending at
address 0x200FF, which may be used
by the programmer for data storage.
Again, this memory map information
is good for the head and is taken care
of for you by a good C compiler.
C8051F120 I/O AND
Even though the Silicon
Laboratories’ CIP- 51 is a proprietary
implementation, it has a standard
8051 program and data address
configuration. A standard 8051
addressing configuration consists of
256 bytes of data RAM, with the
upper 128 bytes being dual-mapped.
Indirect addressing accesses the
upper 128 bytes of general-purpose
RAM, and direct addressing accesses
the 128 byte SFR address space. The
lower 128 bytes of RAM are accessible via direct and indirect addressing.
The first 32 bytes are addressable
as four banks of general-purpose registers, and the next 16 bytes can be byte
addressable or bit addressable. When I first encountered this small segment of
memory, I had to really
think about what was going
on as I was writing my code
in assembler. Don’t get too
caught up in the seeming
complexity as the Keil 8051
C compiler we’ll be using
takes care of us in this area.
What you see in Figure 2
describing the C8051F120
256-byte RAM segment
layout is enough for now.
The standard 8051 configuration
offers a total of four eight-bit ports (0,
1, 2, and 3). The C8051F120 is packaged in a 100-pin TQFP format, which
allows for four additional ports ( 4, 5, 6,
and 7). It is not every day you see a
microcontroller that allows you to configure the actual internal port hardware.
The C8051F120’s general-purpose I/O
operates in an identical manner to the
standard 8051, but better.
Each of the C8051F120’s general-purpose I/O pins can be configured
as either a push-pull or open-drain
output. Power savings wasn’t as big a
deal in the old days as it is now. The
standard 8051 configuration permanently enabled “weak pullups.” The
C8051F120 allows the “weak pullups”
to be globally disabled, allowing
the C8051F120 to play in today’s
low-power application environments.
Take another look at Figure 1. Do
you see all of those on-chip peripherals feeding the Digital Crossbar? The
Digital Crossbar is nothing more than
a large on-chip digital switching
network that allows the mapping of
internal C8051F120 digital system
resources to C8051F120 general-purpose I/O pins on P0, P1, P2, and
■ FIGURE 4. As Grace Slick would say,
“Feed your head.” You can muck around
with your linker to put stuff where you
want it in this space. However, it’s
easier to let the compiler do it for you.
■ FIGURE 3. The bottom line
is that you can configure the
usage of this space to suit you.
April 2007 85