FIGURE 14. Functional
diagram and truth table
of the 74LS240 octal (dual
quad) three-state Schmitt
inverting buffer IC.
Figure 11. Note in
this circuit that
resistor R2 is used
to give the CMOS IC element a
reasonable degree of protection
against damage from excessive
C1 discharge current if a short
circuit suddenly appears acoss the
circuit’s two supply lines.
Figure 12 shows the functional diagram that is common to the
4049UB and 74HC4049 Hex
CMOS inverter ICs. The 4049UB is
an unbuffered type, suitable for
use in linear applications, and the
74HC4049 is a fast, fully buffered
Figure 13 shows the functional diagram and truth table of the
4502B. This is a special-purpose,
three-state Hex inverter in which
the outputs of all six inverters can
be set to the logic 0 state by driving the INHIBIT (pin 12) terminal
high, or can be set to the high-impedance state by driving the
DISABLE (pin 4) terminal high.
The IC can be used as a conventional Hex inverter by grounding
the INHIBIT and DISABLE pins, or
as a normal three-state inverter by
grounding the INHIBIT pin and
applying the three-state control to
the DISABLE terminal.
Finally, Figure 14 shows the
AND gate ICs.
functional diagram and truth table
of the 74LS240 octal three-state Schmitt
inverting buffer IC, in which each buffer
has a fan-out of 30. This IC is actually a
dual quad device, in which inverters 1-4
are controlled via the CA terminal, and
inverters 5-8 are controlled via the CB
terminal. Each of these quads can be
used as a set of normal Schmitt inverters by grounding the control terminal,
or as a ganged set of three-state Schmitt
inverters by using its control terminals
as shown in the truth table.
FIGURE 16. Functional diagram of the 74LS08
or 74HC08 quad two-input AND gate ICs.
FIGURE 17. Functional diagram of the 4081B
quad two-input AND gate IC.
FIGURE 18. Functional diagram of the 74LS11
triple three-input AND gate IC.
70 May 2007
The output of an AND gate goes
high (to logic 1) when all of its inputs
(A, B, and C, etc.) are high. Figure 15
lists basic details of several popular
AND-gate ICs; of these, the 74LS08,
74HC08, and 4081B (see Figures 16
and 17) are quad two input types; the
74LS11 and 4073B (see Figures 18
and 19) are triple three-input types,
and the 74LS21 and 4082B (see
Figures 20 and 21) are dual four
When using AND-gate ICs, each
unwanted gate must be disabled by
shorting all of its inputs together and
tying them to one of the IC’s supply
lines. In CMOS ICs, the shorted inputs
can be wired directly to either supply
line, but in TTL ICs the inputs must (to
give minimum quiescent current consumption with good stability) be tied to
the positive supply rail via a single 1K
resistor, as shown in Figure 22. A single
resistor can be used as a tie point for
large numbers of unwanted inputs.
Sometimes, when using
three or four input AND
gate ICs, you may not want
to use all of a gate’s input
terminals. In this case, the
unwanted inputs can be disabled by either tying them
high (directly in CMOS
gates, or via a 1K resistor in
TTL types) or by simply
shorting them directly to a
used input. Figure 23 shows
examples of three input and
FIGURE 19. Functional diagram of the 4073B
triple three-input AND gate IC.