Logic Analyzer Probes
Probes come in many physical
Clip-on probes are intended for
point-by-point troubleshooting (see
High-density, multi-channel probes
require dedicated connectors on the
circuit board (see Figure B).
The probe shown in Figure C can
acquire high-quality signals and have
a minimal impact on the SUT by
clamping on to existing device
packages. This type of probe is
recommended for applications that
require higher signal density and
reliable connections to your SUT.
FIGURE A. A general-purpose logic
analyzer probe with a 0.025” square
wire-wrap type of pin adapter.
samples data, the higher the resolution
of the resulting measurement. There is
no fixed timing relationship between the
FIGURE B. A high-density multi-channel logic analyzer probe.
target device and the data the logic
analyzer acquires. Use this acquisition
mode when you are concerned with the
timing relationship between SUT signals.
The acquisition mode acquires
the “state” of the SUT. A signal from
the SUT defines the sample point
(when and how often data is
required). The clock signal you use in
the acquisition mode may be:
• The system clock
• A control signal on the bus
• A signal that causes the SUT to change
You sample data on the active
edge, which represents the SUT when
the logic signals are stable. The logic
analyzer samples only when the selected signals are valid. What transpires
between clock events is irrelevant.
FIGURE C. A compression logic
In all instances, the “event”
appears when signals change from
one cycle to the next. You can use
many conditions to trigger your logic
analyzer, such as a specific binary
value on a bus or counter output.
Other triggering choices include:
• Words: Specific logic patterns
defined in binary, hexadecimal, etc.
• Ranges: Events that occur between
a low and high value.
• Counter: The number of events
you program that you are tracking by
• Signal: An external signal such as a
• Glitches: Pulses that occur between
More on Data Acquisition Modes
There are two types of data
acquisition modes: synchronous and
asynchronous. For long, continuous
records of timing details, use the
timing acquisition mode and the
internal (or asynchronous) clock.
Acquiring data exactly as the SUT
sees it requires you to use the state
(synchronous) acquisition mode.
In the state acquisition mode,
the logic analyzer displays each successive state of the SUT sequentially
in a window. You may use any
relevant signal for the external clock
signal for state acquisition.
Triggering selects which data
you capture. Logic analyzer triggering only occurs on digital signals,
and is more sophisticated than
triggering on any oscilloscope.
Logic analyzers can recognize
Boolean operators, such as multiple
signals that are “AND”ed or exclu-sive-”OR”ed together, etc. They can
track SUT logic states and trigger on
conditions within the SUT that
you desire. These may be a simple
transition — intentional or otherwise
— on a single signal line.
If you are chasing an elusive
glitch that occurs when an
Increment or Enable pin becomes
valid, you might want to trigger on
some set of bus-wide conditions that
are known to preceed it. This is a
powerful feature of a logic analyzer.
• Timer: The elapsed time between
two events or the duration of a single
event, tracked by a timer.
• Analog: Use an oscilloscope to
trigger on an analog characteristic and
to cross-trigger the logic analyzer.
With all these trigger conditions
available, it is possible to track down
system errors using a broad search
for state failures, before you refine
your search with increasingly explicit
Ihope this introduction has
taught you a few things about this
powerful benchtop tool — look
forward to more in Part 2! NV