the XC2C64A. All you have to do is
load up the ISE WebPACK on your
PC to use the Platform Cable USB.
Once your PC has recognized the
Platform Cable USB hardware and
installed the Platform Cable USB
drivers, you need only match up the
USB’s JTAG leads to the development
board’s JTAG interface to bring the
XC2C64A to life.
The Xilinx ISE WebPACK allows
you to use the most popular CPLD
programming languages. I’ve chosen
to use ABEL (Advanced Boolean
Expression Language). We could also
use standardized HDLs (Hardware
Description Languages) such as
VHDL (VHSIC [Very High-Speed
Integrated Circuits] Hardware
Description Language) or Verilog to
synthesize our XC2C64A logic. I
selected ABEL as the preferred
language for our XC2C64A project
due to the fact that the ISE
WebPACK contains a comprehensive
built-in ABEL help library. Also, some
very good ABEL tutorials can be had
for a read or a download from our
good friend, the Internet.
At this point, we have our very
own XC2C64 Development Board, a
Xilinx Platform Cable USB CPLD programmer, and Xilinx’s ISE WebPACK.
All we’re lacking is some ABEL logic
statements. So, let’s go to class.
Load up the latest version of ISE
WebPACK and follow along. Rather
than walk you through every detail of
building an XC2C64A project with
WebPACK, I’ve supplied the entire
set of project files we will be
discussing with the XC2C64
download package. To experience
XC2C64A development while
reading this text, all you have to do
is fire up ISE WebPACK and load
the projects I’ve provided in the
If you’re not a seasoned CPLD
user, you will need some learning
curve time with ISE WebPACK. The
best way to get up to speed with it is
to simply load a project in and play
it. Once you become familiar with
WebPACK and you get your development board hardware online, you can
burn the supplied applications into
your XC2C64A and try them out on
your XC2C64A hardware.
The most complex of logic ICs
track their heritage back to basic forms
of logic hardware such as AND, OR,
NAND, and NOR gates. So, it is fitting
that our very first XC2C64A code be
that of a simple two-input AND gate.
With that, let’s put together some
AND gate ABEL code.
Usually, declarations follow the
module keyword and the module
name. The keyword DECLARATIONS
is implied when declarations follow
the MODULE keyword-module
name statement. However, ad hoc
declarations can be made anywhere
in the ABEL code module as long
as the DECLARATIONS keyword
precedes them. Let’s use the classic
method of declaring and define our
AND gate inputs and output:
outputC PIN istype ‘com’;
BUILDING AN AND GATE
If you’ve just picked up this
magazine and this is your first read
through, odds are that you don’t
have any XC2C64A hardware built
up at this point in time. That’s okay.
An ABEL-based code module
begins with a module statement. The
module statement consists of the
module keyword (MODULE) followed
by a module name. Let’s call our
module and_gate. This is what our AND
gate ABEL code looks like at this point:
This looks a lot like C, doesn’t it?
Think about the code in terms of a
physical AND gate. We have a pair of
inputs and an output. The ‘com’ tells
the compiler that the output pin is a
result of a combinatorial operation.
Combinatorial simply means that the
result is derived from a combination
of mathematical terms such as our
AND gate inputs inputA and inputB.
We can also assign XC2C64A pin
numbers to the input and output pins
at this time. However, the pin numbers
are automatically assigned in the
XC2C64A implementation process
and it is recommended to allow the
automatic pin assignments to override
your human pin assignment logic.
The reasoning behind letting the
software do the pin assignments lies
in the software’s ability to optimize
the pin assignments to the logic that
is generated inside of the XC2C64A’s
FBs. The Xilinx documentation also
states that it took some really smart
CPLD engineers 12 years to get to
this point with the pin assignment
automation. (That statement kinda
■ PHOTO 3. I originally purchased a
JTAG programming cable, which
required a parallel port interface.
After discovering that my new laptop
doesn’t have a parallel printer
interface, I got my hands on the
Xilinx Platform Cable USB JTAG
programming device you see here.
You can get your own Platform
Cable USB programming device from
Digi-Key. The other end of the cable
plugs pin-for-pin into the XC2C64
development board’s JTAG interface.