TO FPGA LOGIC
TO FPGA LOGIC
■ FIGURE 2. From a user/programmer standpoint, these
FPGAs aren’t as complicated as one might think. Buffers,
clocks, multiplexers, and latches are common logic
building blocks that I’m sure all of you understand. What
you don’t see here are the pull-up/pull-down and ESD
components at the input buffer input.
CLB to Figure 1 illustrates the CLB concept.
Translating the Xilinx speak to Figure 1 graphics, the
Xilinx “function generators” are actually the look-up table.
In terms of an FPGA, a register is synonymous with a latch
or a flip-flop. In the case of Figure 1, the Xilinx register is
our LUT’s D flip-flop. Reprogrammable routing control is a
fancy way of saying multiplexer. Our LUT’s reprogrammable
routing control is represented in Figure 1 by the two-input
multiplexer at the LUT output.
CLBs are the physical foundation that all Xilinx FPGA
designs are built upon. All of the software-generated logical
functions are implemented by CLBs. In the Xilinx FPGA we
will be working with, a CLB is a wee bit more complex
than our simple LUT in Figure 1. A CLB is made up of four
interconnected slices. Each slice consists of a pair of
LUTs and two dedicated storage elements that can act as
flip-flops or latches. One pair of LUTs supports logic and
memory functions within the slice. The remaining LUTs in
the slice service logic only. This logical arrangement of
slices allows the LUTs to be used as 16x1 memory or as
16-bit shift registers.
We will be working with two Xilinx Spartan-3A FPGAs:
the XC3S700A and the XC3S50A. The plan is to cut our
FPGA teeth with the larger 700A and design our own
FPGA hardware with the smaller 50A. To give you a feel
for the FPGA size difference, the BGA-packaged 700A
contains 1,472 CLBs and 700,000 system gates while the
much smaller 144-pin 50A has but 176 CLBs and 50,000
system gates. We’re going with the smaller Spartan-3A
FPGA for our hardware design because it is housed in a
solder-friendly 144-pin TQFP package.
The whole idea of using an FPGA in an electronic
circuit of our design would be null and void if we were
unable to access the internal logic of the FPGA.
The physical I/O pins of our Xilinx FPGAs are all
tied internally to IOBs (Input/Output Blocks).
Think of an IOB as a programmable unidirectional
or bidirectional I/O interface to the FPGA’s logic
blocks. A typical Xilinx IOB has three data paths.
On the input path, the logic signal presented at
the FPGA pin is routed through an internal buffer
that feeds a programmable delay mechanism. The
output of the programmable delay block can be
routed directly to the FPGA logic or through a
latch and then out to the FPGA logic. A simplified
block diagram of the FPGA input path is shown
in Figure 2.
The second and third data paths work
cooperatively to form a programmable output
path, which has the ability to be coaxed into high
impedance or tri-state mode. Figure 3 gives us an
FPGA I/O PIN
■ FIGURE 3. This graphic is greatly simplified as
you really only need to understand the concept.
There are actually two storage blocks available
in each output path. In addition, the same
pull-up/pull-down and ESD circuitry that is made
available to the input path is also available to
the output path.