ADVANCED TECHNIQUES FOR DESIGN ENGINEERS
■ BY FRED EADY
ROLL YOUR OWN FPGA DESIGN
TO REALLY GET TO KNOW A MICROCONTROLLER, CPLD, OR FPGA, one may
take the programming and hardware design knowledge gleaned from a factory-generated development kit and apply it to a unique personal application. We’ve
paid our dues with a factory Xilinx FPGA development board. So, our goal this
month is to get down and dirty with our own Xilinx XC3S50A FPGA design.
For the past 60 days or so, I’ve been glued to the
XC3S50A datasheet and user’s guide. In that time,
I’ve come to terms with what it takes to put an FPGA like
this to work from the hardware and firmware perspectives.
I’m going to show you how to take the bare home-brewed
50A development board you see in Photo 1 from concept
to reality. To best understand the 50A and its supporting
components, I’ll break the FPGA hardware and firmware
into smaller modules that can be easily digested and
understood. A good place to start is with the power supply.
POWERING UP THE XC3S50A
The XC3S50A operates with a trio of power supply
voltages. The hardware core requires a regulated 1.2 volt
power source. A separate VCCAUX power supply voltage
is used to drive the JTAG interface. For the Spartan-3A
devices, VCCAUX voltage levels can be implemented as
either 2.5 or 3. 3 volts. With JTAG hardware, things get
easier when we choose to power the 50A’s VCCAUX pins
with 3. 3 volts. The I/O pins are driven by the VCCO
power rail. For the purposes of our design, all of our I/O
will be 3. 3 volt compatible. Thus, the VCCO power
supply will be designed to provide 3. 3 volts.
I wanted to keep the power supply as simple as
possible. At the same time, I also wanted to design
in a power supply system with components that are
intended for use with an FPGA. That means I will
avoid using run-of-the-mill 7805 and LM317 circuits.
The LDO (low dropout) voltage regulators I’ve
outlined in Schematic 1 are intended to be used in
battery-powered applications, which may include
FPGAs and microcontrollers. As you can see in the
power supply schematic, all of the LDO voltage regulators
require a minimum of external components.
The LP38855 provides the FPGA’s 1.2 volt core
supply voltage. Being available in standard voltages of 0.8
and 1.2 volts puts the LP38855 squarely into the FPGA
application arena. It can supply up to 1.5 amperes of
current and only requires 10 μF ceramic capacitors on its
input and output pins. The key to a stable LP38855 design
lies in the selection of the input and output capacitors.
The 10 μF, X7R ceramic capacitors are required for
stability. However, once they are in place, we can hang
unlimited additional capacitance on the LP38855’s input
and output pins in parallel with the ceramic capacitors. I
chose to add a 220 μF tantalum output capacitor to my
1.2 volt design. In addition to the 10 μF ceramic input and
output capacitors, the regulator also requires a good
quality 1 μF capacitor between its BIAS pin and ground.
Since the LP38855 datasheet recommended a
ceramic BIAS capacitor, I designed in an X7R 1.0 μF
ceramic capacitor. Note that the ENABLE pin is tied to
the BIAS and INPUT pins since we don’t have a need to
disable the output. The LP38855 variant I used in this
■ PHOTO 1. Putting down the project parts won’t be
as difficult as it may seem from this perspective. The
only “tight” soldering that we will have to do is
performed on the Platform Flash IC. Even with that,
we can still hand–solder every part on the board.
September 2008 67