■ PHOTO 4. This shot is an overhead view of the XC3S50A
JTAG interface hardware and the 1 Mbit Xilinx Platform
Flash PROM (U1) that is used to boot the 50A. The PROM is
enabled and selected by the position of the CE (Chip Enable)
jumper. The PROG_B pushbutton is actually the FPGA reset
button that prompts the PROM to reload the configuration.
we have to do is lay in a JTAG interface on our garage-built development board.
The entire JTAG hardware interface is part of
Schematic 2. You can see the actual JTAG hardware in
Photo 4. The only new trick we employ with this JTAG
interface that we did not pull out of our CPLD hat is the
addition of a Xilinx Platform Flash PROM, which is included
as part of the now two-device (XC3S50A and XCF01S
Platform Flash) JTAG programming chain. The XCF01S is
woven into the JTAG chain by redirecting the 50A’s TDO
(JTAG Serial Data Out) line to the XCF01S’s TDI (JTAG
Serial Data In) pin. The XCF01S’s TDO pin is then routed
to the JTAG programming connector’s TDO pin, which
completes the JTAG programming chain.
The PROG_B pushbutton performs the same task as a
microcontroller’s reset pushbutton. Depressing the PROG_B
pushbutton will force the 50A to drive its INIT_B pin logically
low and enter master reset mode. The alternate way to enter
master reset mode and drive the INIT_B pin logically low
is to repower the chip. During the time that the INIT_B pin
is low, the 50A is performing what is termed FPGA
housecleaning. “Housecleaning” here is the act of clearing
internal configuration memory. The INIT LED illuminates
during this process. Once the 50A is loaded, the INIT_B
pin can be configured to drive logically low in the event of
a CRC error. The DONE pin is driven logically high when
all of the configuration data has been successfully loaded.
A successful configuration data load is signaled by the
illumination of the DONE LED and inactive INIT LED.
If we wish to program the 50A from the JTAG
interface, we must place a jumper across the M1 mode
select pins. We must also instruct ISE WebPACK to assign
the startup clock to the JTAG interface. Placing jumpers on
M0, M1, and M2 puts the chip into Master Serial mode,
which forces it to generate a clock signal on its CCLK pin.
In Master Serial mode, the CCLK clock signal drives the
XCF01S PROM to read its configuration data. The startup
clock value in ISE WebPACK must be set to CCLK in
Master Serial mode. The mode jumpers can configure the
50A for slave modes, as well. However, our 50A design
does not include any slave mode hardware. Our mode
select hardware can be seen in Photo 5.
The XCF01S PROM’s DO (Data Out) pin can be
permanently enabled by grounding the XCF01S’s CE (Chip
Enable) pin. This is useful if we have a need to access the
contents of the XCF01S after the configuration data has
been downloaded. We can also choose to jumper the
■ PHOTO 6. Resistor R10 is acting as an auxiliary external
pullup to assist the INIT_B pin’s weak internal pullup. The
INIT LED will illuminate dimly upon successful configuration
download unless you instruct ISE WebPACK to pull up the
INIT_B pin after the configuration download.
THE DESIGN CYCLE
XCF01S PROM’s CE pin to only be active while the 50A
DONE pin is being driven logically low. Doing this only
allows the XCF01S to regurgitate the extent of the
configuration data. No post-configuration XCF01S access
is permitted as the DONE pin is driven logically high at
the end of the configuration data download process.
If you’re wondering how we get that configuration
data into the XCF01S in the first place, no worries. We tell
ISE WebPACK to generate a pair of configuration files that
can be loaded into the XCF01S and the XC3S50A. If our
hardware is connected correctly to the JTAG chain, the ISE
WebPACK iMPACT programming application and the
program cable USB programmer are able to see both of
JTAG devices. With that, we are able to tell iMPACT which
device and which configuration file we want to load via
the JTAG connection.
The actual XCF01S Platform Flash IC and supporting
hardware are represented in Photo 4. Schematic 2 holds
the logical XCF01S presentation. The DONE and INIT
status hardware is shown in Photo 6.
■ PHOTO 5. Unless you decide to add some slave memory
devices, we’ll only jumper M1 for JTAG mode operation and
all of the mode jumpers for master serial mode operation.
September 2008 71