THE DESIGN CYCLE
■ SCREENSHOT 1. I used the excellent CAD capabilities
built into ExpressPCB to build the ZG2100M
pad farm and no-trace area.
communicating with external devices and programmers
that support the JTAG standard. There is also a UART
interface that is primarily intended for use in a test
environment. Our design will not employ the services
of the ZG2100M’s JTAG interface and we will not
invoke a trace from the ZG2100M’s UART. As you can
see in Schematic 1, the JTAG interface is held at bay by
pulling the ZG2100M’s JTAG_RST_N and JTAG_EN I/O
pins logically low.
To enable us to use the ZG2100M drivers in the
Microchip TCP/IP stack, we must connect our
PIC24FJ128GA006 to the ZG2100M as directed by
Figure 1. Well, almost. The connections you see in
Figure 1 are intended for a 100-pin PIC24FJ128GA010.
The ZG2100M’s CSN pin acts as the SPI portal
chip select and is actually attached to the
PIC24FJ128GA006’s RB2 I/O pin. Take another look at
Schematic 1 and you’ll see that the SPI 1 portal’s SCK1
pin actually shares I/O pin RF6 on the
PIC24FJ128GA006, as well as the PIC24FJ128GA010.
That’s where the PIC24FJ128GA006 and
PIC24FJ128GA010 SPI I/O pins part ways. The
PIC24FJ128GA006’s SDI1 and SDO1 SPI I/O pins are
shared by the RF2 and RF3 I/O pins, respectively.
The ZG2100M uses an interrupt to trigger data
communication event handlers in the PIC24FJ128GA006
firmware. Note that INT1 is actually sharing I/O pin RD8
on the PIC24FJ128GA006. In that I/O pins RF0 and RF1
are used in their native fashion, we simply connect the
RF0 and RF1 I/O pins per Figure 1 just as we did with I/O
That does it for the PIC24FJ128GA006-to-ZG2100M
interface. Believe it or not, that’s all you really need to
know about the Wi-Fi module if you use the Microchip
TCP/IP stack to drive the ZeroG module. With that, let’s
take a walk around the PIC24FJ128GA006.
PIC24FJ128GA006 ODDS AND ENDS
2. 5 volt regulator. The PIC’s internal 2. 5 volt regulator’s
stability is assured by the presence of C4 — (a 10 µF
ceramic capacitor) and C3 (a 100 nF bypass capacitor)
which are both housed in 0805 SMT packages.
I could have easily left the pair of NUD3105 MOSFET
drivers out of this design as the PIC24FJ128GA006 can
easily handle driving LED0 and LED1 directly. However,
adding Q1 and Q2 allows you to drive inductive and
noninductive loads up to 500 mA from the PIC I/O pins if
I incorporated the TC1262-3.3 into the design to allow
you to power the PIC24FJ128GA006 and ZG2100M with
a standard 5.0 volt wall wart. I found that I could actually
power the circuitry with a 3. 3 volt wall wart, as well.
There’s no magic at the 8 MHz interface. By
designing in an 8 MHz crystal, the PIC24FJ128GA006 can
use its 4x PLL to run at 32 MHz if the programmer
Okay. Now that you’re checked out on the ZG2100M
MCLR pullup resistor R5 is the beginning of
a standard PIC24FJ128GA006 ICSP
programming/debugging setup with supporting
ICSP connections at I/O pins RB6 and RB7. The
100 nF (0.1 µF) power supply bypass capacitors
C5, C6, C7, and C8 are standard and necessary
add-ons for any PIC.
■ SCREENSHOT 2. Here’s what the
ZeroG - PIC24FJ128GA006 Trainer printed circuit
board looks like before we add the upper and
lower layer ground planes. The PIC24FJ128GA006
I/O pads are on 0.1 inch centers to allow the
ZeroG - PIC24FJ128GA006 Trainer to plug into a
similar pitched auxiliary board.
April 2010 71