■ SCREENSHOT 3. The logic has been voiced and the
connections have been made. All that's left to do is run
the C code that was generated by this screenshot.
CLC DESIGNER BASICS
Let’s attach an external signal coming in on CLC1 IN1
to GATE 1 and pass it through an AND-OR logic block. We’ll
extract the output signal at the CLC1 output. Basically, what
comes into CLC1 IN1 appears at the CLC1 output, which
we will allow to be presented on a PIC16(L)F1507 I/O pin.
If you consult the PIC16(L)F1507 datasheet, you’ll find that
CLC1 IN1 is associated with RC7, and CLC1 appears on I/O
pin RA2. If you’re wondering why we didn’t come in on CLC1
IN0, take a look at Schematic 1 and recall my First Rule of
Embedded Computing which says that nothing is free.
In our application, I/O pin RA3 is
being used as the MCLR pin. So, if we
want to designate an external input for
CLC1, we must use CLC1 IN1. Going
with what we know at the moment, we
will select CLC1 IN1 (RC7) as the external
input source for GATE 1. A mouse click
on the “x” associated with CLC1 IN1
makes the “connection” with GATE 1.
Let’s stop here and use Screenshot
1 to analyze what will or will not
happen. GATE 1 is an OR gate. Any
logically high input applied to any of
GATE 1’s inputs will result in a logical
high on the output of GATE 1. CLC
Designer forces the output of any GATE
with no assigned inputs as logically low.
If we apply a logical high to CLC1 IN1,
GATE 1’s output will go logically high.
Since there are no inputs attached to
In that GATE 2’s output is logically low, the output of
the AND gate will also be driven logically low regardless of
GATE 1’s output logic level. As you can see in Screenshot 1,
the output of both AND gates feeding the final OR gate is
logically low. Thus, a logical low level is seen at the CLC1
buffer output. That’s not what we want.
To pass the CLC1 IN1 logic level through the AND gate,
we must force GATE 2’s output logically high. That’s easily
done by simply clicking on the GATE 2 output. An inversion
symbol is attached to the output of GATE 2, transforming it
into a NOR gate with a logically high output state. To pass
the CLC1 IN1 logic level to RA2 (CLC1 output), we must
enable the CLC1 output. Plus, we need to make
sure that CLC1 is enabled. Both of the
aforementioned operations are easily performed
with a couple of mouse clicks on the Output
Enable and CLC Enable check boxes.
The CLC Designer’s computed CLC register
entries can be displayed by clicking the Copy and
Show button. We can also enter some descriptive
comments at this time in the Comments window.
Finally, we save the final template information
shown in Screenshot 3 as a C include file. We’ll
call it pushbutton-clc.inc. The nature of the
filename will become obvious shortly. Here’s the
C code we generated using CLC Designer:
// File: pushbutton-clc.inc
// Generated by CLC Designer, Version:
// Date: 12/15/2011 3:30 PM
// INPUT = RC7
■ PHOTO 1. Power supply, oscilloscope,
voltmeter, power supply, and logic
analyzer — all in less space than a laptop PC.