58 October 2013
generator whose output pins are also part of JP12. The
gate and drain of an extra 24 volts 1A FET tops off the
JP12 pinout. A visual of JP12 is provided in Photo 5.
Photo 6 covers a lot of territory. The 16 differential
encoder inputs are located across the very top of the shot.
The first eight differential encoder inputs communicate
with the KFLOP via a short ribbon cable connected to the
Kanalog JP14 connector. The second set of eight
differential encoder inputs communicate by way of the
RJ- 45 terminated silver satin cable.
The FET relay drivers are accessed via JP8 at the far
right. Each FET is rated for 24 volts one amp. The FETs
are wired to provide a ground at the SWx pins when the
associated I/O bit is activated. There’s no rocket science
here. A positive power supply is connected to one side of
the relay coil and the other side of the relay coil attaches
to an SWx pin. Kanalog does not include a reverse diode
for the relay.
So, we must be sure to install the reverse diode across
the relay coil to prevent damage to the Kanalog circuitry.
If the FET switch is not driving an inductive load, the
reverse diode is not necessary.
The Kanalog ADC inputs and digital-to-analog
converter (DAC) outputs are rated for ± 10 volts.
The ± 10 volt levels are common to CNC control and
monitoring peripherals. Photo 7 lays out the ADC
; Photo 5. JP12 is the Kanalog non-isolated GPIO interface
point. We can also access the 3. 3 volt and 5.0 volt power
rails via JP12.
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