FIGURE 1. A 2-to- 4 line binary decoder
with Enable truth table.
New source file.
click Finish. When it
asks to create the src directory, click Yes.
Okay, okay. I know you’re chomping at the
bit to start coding, but there is only one more
step I promise! Select binary_decoder in the
Implementation Hierarchy, look below at the
Processes tree, and right-click on Generate
Programming File. Select Process Properties,
check Create Binary Configuration File, and
click OK. Done! Let’s write some hardware!
PHOTO 1. Mojo V3.
Lastly, verify that “Verilog” is selected as the
Preferred Language. Click Next (Screenshot 2).
Click Finish on the next window, titled Project
Okay, don’t get mad, but ... I may have lied
to you back there. Before we can start coding,
we need to first look at the truth table for a 2-
to- 4 line single bit decoder (Figure 1). It’s pretty
simple, really. The two-bit binary input, A,
corresponds to a specific bit in D, which is four
bits wide. For example, an input of A = 10 and
EN = 1 creates an output of D = 0100. In other
words, A = 2 corresponds to D2 = 1. The logic
gate diagram for the truth table is shown in
Figure 2. This is pretty easy to write in Verilog,
so let’s do it! Copy the following Verilog code
into the source file we just created —
As stated, we’ll be designing a 2-to- 4 line
single bit decoder with Enable. Let’s create the
// gate-level 2-to-4 line decoder
// with enable
Verilog source for the decoder. Create a new
source (Project->New Source), select Verilog
Module, and name the file binary_decoder. Add
/src to the end of the Location and click Next
(Screenshot 3). At
the next window —
titled Define Module
input wire en,
input wire [1:0] a,
output wire [3:0] d
— just go ahead and
click Next; we’ll
define our I/O ports
later. In the
36 July 2015