12 December 2015
n FIGURE 6.
AGood question, John! I cannot write a complete article in this
column due to space
constraints (maybe Ryan
Clarke can write a follow-up
article on CPLDs and PALs),
CPLD stands for Complex Programmable Logic Device
and FPGA stands for Field Programmable Gate Array.
Figure 6 shows the architecture of an FPGA which
consists of programmable interconnects,
logical blocks (consists of look-up tables,
flip-flops, and a routing matrix), and Input/
Output (I/O) blocks. The FPGA user programs
the interconnects to “wire” the logical blocks
using the look-up tables and routing matrix in
a fashion which produces a specific output for
a given input (e.g., an input of 0001000 may
produce an output of 10010001).
Look at Figure 7 for a simplified FPGA
logical block based on AND gates. Figure 8
shows the FPGA logical block after the user
has programmed the interconnects with the
FPGA truth table in Figure 9.
A real FPGA project is much more
complex than my example, but you should
get the idea. The FPGA manufacturers provide
Integrated Synthesis Environment (ISE)
software which allows you to
program your FPGA logical
blocks via a PC using keyboard
symbols. Then, the program
can be coiled on the PC and
downloaded to an FPGA
I remember in a training
seminar having to create a
logic circuit using the basic
gates (AND, OR, NAND,
NOR, and flip-flops) that would
read out the numbers of my
birthday when I pushed a
switch. This took a couple of
12 hour days and the board
looked like a rat’s nest with
so many wires. Then, we
used FPGAs to produce the
same result. I already had the
truth table from the previous
project which took only 30
minutes to derive, so the FPGA
programming, compilation, and download took less than
15 minutes. WOW!!!
In Figure 10, I have a CPLD block diagram. The
MC is a macrocell which performs combinational and
sequential logic, complementing, and feedback functions.
In essence, the CPLD is an FPGA without the look-up
tables and complex functionality. CPLD manufacturers
provide software programming aids like the FPGA ISE.
CPLDs and FPGAs with JTAG (Joint Test Action Group)
ports can be programmed using the same JTAG compatible
Comparing FPGAs and CPLDs: FPGAs do not store
their configurations which must be reloaded every time the
n FIGURE 7.
n FIGURE 9.
n FIGURE 8.
n FIGURE 6.