What is OpenCores.org?
OpenCores.org is the leading website related to
open source hardware IP (intellectual property) cores for
FPGAs (field programmable gate arrays). On the site are
hundreds of downloadable IP cores ranging from simple
memory modules to a fully functional Amiga Original
Chip Set System on Chip (SoC) incorporating the
Wishbone Bus. The site does require you to create an
account in order to download IP-cores from their SVN
repositories, but the process is relatively simple and they
also provide you with a free email alias.
Of course, just like open source software, the quality
of the open source IP cores can be very different. While
some cores may be wonderfully documented with full
support from their authors, others are barely functional
with the user left guessing how it works, if at all! As with
anything free on the Internet, your mileage may vary.
The challenge of using a third-party IP core is how to
integrate it into your chosen FPGA platform. The goal of
this article is to take a fully functional and complete core
from OpenCores.org and integrate it onto the Mojo V3
development board. Let’s get started!
What Should We Create?
While the allure of the Amiga SoC is strong, we
should probably start with something a little more tangible
and a bit simpler to test and verify. How about a 16 x
eight-bit SPI serial ROM, you say? Okay!
In order to interface with and test this ROM, I used a
Microchip PIC24FJ64GB002 microcontroller installed on
the Microstick II development board. Why not an Arduino,
you ask? Well, the Arduino Uno R3 I own is a 5V device
and the Mojo V3 is a 3.3V device.
Additionally, I prefer PICs, and frankly, I’ve been
waiting for an excuse to use the Microstick II in a project.
Feel free to use any other platform that is 3.3V
Our SPI serial ROM will use all four of the standard
SPI signals (SCK, MOSI, MISO, and SS). The ROM will
output the data stored at a saved ROM read address and
subsequently increment that saved address upon the
completion of each SPI transfer. It will also respond to a
single command which will set the saved ROM read
address for a subsequent read operation. This should be
fairly simple to design, so let’s get on it!
Prior Planning Before Execution
First, let’s take a look at the actual ROM
(rom_16x8.v). The signals for the ROM are as shown in
I’ve designed it as a synchronous ROM, and stored a
classic and appropriate message inside. Of course, that
message would be, “Hello, World!” There really isn’t much
more to say about such a simple module, so let’s move on.
Poking around OpenCores.org, I found a very well
constructed SPI core which includes both master and
slave modules. The core — titled SPI Master/Slave Interface
— was designed by Jonny Doin and is listed as stable. The
overview page for the project is detailed and has
screenshots of waveforms showing how the master and
slave modules function. Perfect! This is a great example of
an above average IP core on OpenCores.org.
Of note, the source for the SPI Master/Slave Interface
is written in VHDL. Our project is written in Verilog.
However, even though you may not know VHDL (such as
myself!), it is easy to integrate modules written in different
HDLs (hardware description languages).
Let’s take a look at the source code available at the
article link for the SPI slave (spi_slave.vhd). The
comments are thorough and do a nice job outlining how
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clk Master Clock
addr Four-bit Address
data Eight-bit Data
clk_i Master Clock
spi_sck_i SPI Clock
spi_mosi_i SPI Master Output/Slave Input
spi_miso_o SPI Master Input/Slave Output
spi_ssel_i SPI Slave Select
di_req_o Input Data Request
di_i N-bit Input Data
wren_i Input Write Enable
wr_ack_o Input Write Acknowledge
do_valid_o Output Data Valid
do_o N-bit Output Data
By Ryan Clarke KJ6MSG Post comments on this article and find any associated files and/or downloads at