The code for the PIC24FJ64GB002 on the Microstick
II and the Mojo V3 is available for download at the article
link. I soldered a right-angle header to J6 of the Microstick
II, which connects to pins 21 and 22 for use with the
UART module. You will need a 3.3V TTL serial cable to
interface with your computer. I used a SparkFun FTDI
The test software is simple to use. It accepts three
d — Dump ROM contents to screen.
r — Read byte from current ROM read address.
a=addr — Set ROM read address to <addr>; a base- 10
number from 0-15.
You can see from Screenshot 2
that everything works as expected.
Where Do We Go from
The OpenCores website has
many different cores available, as we
discussed at the beginning of the
article. One neat feature to explore
is the Wishbone Bus. This is an
open source bus architecture
specifically designed to facilitate
communication between IP cores
on an FPGA for SoC design. Many
of the cores on the site use the
Wishbone Bus. Take a look around
and find something to hack with.
Until next time, I hope you
continue to enjoy the interesting,
albeit complex world of FPGAs!
52 July 2016
OpenCores.org SPI Master/Slave
Micro Mojo V3