We finally get to the
frequency counter. Here, I
implement a technique I used in
an earlier Nuts & Volts article on
frequency counters (March 2015).
The common hobbyist frequency
counter design sets up a fixed
gate interval (say, one second)
and then counts the number of
input cycles during that interval.
With a one second gate, the
number of input cycles is equal to
the input frequency with a ±1
cycle resolution. This works very
well if the input frequency is high
because the ±1 count error can
be ignored. However, at low
frequencies, the ±1 count error
can be very significant.
To accurately measure a low
input frequency, the gate interval must be increased, or
the counter can measure the period of the input signal. In
my design, I automatically switch to a period
measurement when the input frequency is less than
150,000 Hz. This is discussed in detail below.
In the VVR mode (see Figure 2), the PIC sets the
VVRMode bit which — with relay K1 — configures the
DAC0800/LM6181 pair for zero volts output when the
PIC outputs binary 00000000 on port D, and + 10 volts for
If we use
00000000 as a
starting point, there
are then 255
voltage steps to get
to + 10 volts.
step is 10/255 or
0.0392 volts. This is
an awkward value
since it leads to
For example, if we
want a 5. 2 volt
output, we need a
buss digital value
of 5.2/0.0392 or
133 it produces
133 x 0.0392 or
5.216 volts — a .3% error.
I get rid of this error by simply using 250 as the
number of steps to 10 volts, so the voltage per step is
10/250 or exactly 0.040 volts. Now, the 5. 2 volt setting is
5.2/0.040 or 130, exactly 5. 2 volts. This works for all
voltages that have an even number for the fractional part
( 5.0, 5. 2, 5. 4, etc.).
With an odd fractional part like 5. 3 volts, the setting is
5.3/0.0400 or 132.5, and all voltages with an odd
fractional value will have a half bit remainder. I correct this
error by using a HALFSTEP control line on the PIC which
effectively adds a ninth bit to the DAC0800. This is shown
at the right in Figure 2. If HALFSTEP is set high, the 2. 4
November 2016 29
■ FIGURE 1.
■ FIGURE 2. Digital-to-analog converter