interference, I turn the
oscillator off in the
U2 is a 74F153
dual 4-to-1 multiplexer
that is controlled by the
PIC via the Select (SA,
SB) lines as follows:
00. Used in normal
mode (SIGIN from
01. Used in frequency
counter mode (SIGIN
from input amplifier
divided by four).
10. Used in PFG mode
with clock from high speed oscillator (HSCLK).
11. Used in PFG mode with clock directly from the PIC
U2a sets the clock input to the eight-bit counter (U3)
to one of the following inputs:
00. Frequency counter input (SIGIN from input amplifier).
01. Frequency counter input (SIGIN from input amplifier).
10. High speed clock (HSCLK).
11. Clock from PIC (PICCLK).
U2b sets the input to the frequency input pin on the PIC
(RC0) to one of the following inputs:
00. The clock pin on the eight-bit counter (U3-CP).
01. The second stage output on the eight-bit counter (U3
10. The clock pin on the eight-bit counter (U3-CP).
11. The clock pin on the eight-bit counter (U3-CP).
I chose the PIC18F452 (see Figure 4) for this project
for several reasons.
Its internal clock operates at 40 MHz, giving a 100
nanosecond instruction time. This is important when the
frequency counter is operating in the period measurement
mode or when you want to implement the PFG directly
from the PIC (bypassing the RAM).
Because this PIC has a PLL that multiplies the crystal
frequency by four, a 10 MHz crystal can be used. This
reduces radiation that might interfere with the frequency
counter input amplifier. The accuracy of the frequency
counter is entirely dependent on the accuracy of the
crystal. A typical crystal has an accuracy at room
temperature of about 100 PPM (parts per million); in
other words, one in 10,000.
Many temperature controlled 10 MHz oscillators with
one in 1,000,000 or better accuracy are available online at
High Speed Oscillator
Figure 5 is the schematic for the high speed oscillator.
It is basically a square wave relaxation oscillator using a
74AHC04 high speed hex inverter that will operate at a
maximum frequency of about 15 MHz. The output
(HCCLK) drives the eight-bit RAM clock input in the
multiplexer ‘ 10’ position (the normal PFG mode). At 15
MHz, the output of the PFG with 64-bit resolution is
15,000,000/256 or about 58 kHz.
The output frequency of the oscillator is set by the
band switch (SW5) and the two front panel
potentiometers R22 and R23. The oscillator is turned off
(via SELINB) when in the frequency counter mode.
The software for this project was written in C using
the microC development package, but any C compiler
would work fine. The commented source code can be
downloaded from the article link.
Photo 1 shows the layout of the front panel. On the
left are the two voltage selectors for the VVR: one (SW2)
for volts and the other (SW3) for tenth volts. The output of
the VVR appears on the two banana jacks (VVR/PFG
November 2016 33
■ FIGURE 5.