containing the character.
The code for keyboard input supports the core
functions (all characters, shift, backspace, enter, escape)
necessary for this project without taking up too much
code space, and without using interrupts. It works well
with a 4 MHz clock speed as long as you are not a super-fast typist. See the comments in the code at the article
link for more on how it works.
CPU communication with external memory consists
of an address bus to select the required byte, a data bus
to either read or write that byte, a chip select signal to
activate only the desired chip on the bus, and read and
write signals to tell the memory chip whether to send or
receive data. The CPU starts by placing the address on the
memory chip’s address inputs, and then places data on
the data bus (for a write) or sets its data bus pins to inputs
to read data. The desired memory chip is activated with its
individual chip select input, and then its read or write
input is activated to complete the transfer.
The order and timing of these steps is specified in the
datasheet for each type of memory chip (see References).
This project uses a 62256 32 kilobyte static RAM and a
27C256 32 kilobyte EPROM. The EPROM can be hard to
find as a new part, so use one from your collection of
vintage chips. Address bit A15 is used to handle the chip
select signal for the two memory devices through an
inverter logic gate, so one or the other chip is always
selected. Address bits A0-A14 then select the byte within
the selected chip. This means that sending the 16-bit
address handles the chip select and byte address
simultaneously, which is okay if you respect the overall
signal timings for the chip.
The read and write signals are generated with the
PIC’s PortE: a three-bit port that drives a 74HC138 three-to-eight decoder chip. Until the memory chip receives a
read or write signal, its data bus connections are internally
disconnected or “tri-stated” so they do not interfere with
data transfers with other chips on the bus. When the
signal is received, the selected memory chip accepts the
data on the bus for a write, or places the data from the
selected address on the bus for a read. I’ve placed a
“Data” LED on output 0 of the decoder which will flicker
when data is being transferred; it can also be used to send
blink codes to the user.
From the PIC’s perspective, the PortC address bus and
the PortE decoder bus are always outputs, but the PortD
data bus must rapidly switch between outputs and inputs
as necessary throughout the code. Look for lots of trisd =
255 and trisd = 0 statements in the code in the data
transfer subroutines. Also look for the address latch
operation that presents the 16-bit address to the bus as
two separate bytes — similar to the way the old CDP1802
microprocessor and some others addressed their memory.
Latch and LCD
A true CPU can only use its data bus pins to drive the
inputs of other logic chips because they are a “logic level”
interface that has almost no capacity to supply current.
They cannot directly control an LED, serial port, or any
other device in the “real world.” In addition, since the data
bus is usually busy talking to the memory, it cannot afford
to be tied up with those functions. A variety of interface
chips usually share the data bus to provide the necessary
real world connections and free up the bus. Interface
chips have their own read, write, and enable inputs, and
are generally accessed similarly to memory chips except
that they usually don’t use the address bus.
In this design, a 74HC574 octal latch acts as a simple
output-only interface chip on the data bus. To use it, the
PIC places a byte on the data bus and uses the 74HC138
decoder to send a pulse to the latch’s clock pulse input.
The data is then available on the latch’s outputs and is no
longer just “data,” but can be used to control real world
The alphanumeric LCD in the project also acts a lot
like a latch on the data bus. The HD44780 compatible
display controller has an eight-bit data interface, a
read/write input, an “RS” input which tells the controller
whether the data on the bus is text to be displayed or a
command to be executed (such as clearing the display),
and an “E” input that latches the data into the controller.
The RS input can be shared with address line A7 to save a
pin on the PIC since you will never being accessing the
memory at the same time you are writing to the LCD. The
74HC138 decoder’s active-low output drives the LCD’s
active-high E latch input through an inverter. The high-level
LCD control commands available in various PIC
January 2017 29
“Legacy Communication with the 32-bit Micro
Experimenter,” Nuts & Volts, October 2011
Retro microcomputer designs using the Z80
Retro microcomputer designs using the CDP1802
Description of PS/2 keyboard protocols
62256 SRAM datasheet
27C256 EPROM datasheet