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to USB devices, and much more (visit www.zilog.com to
check the full product line).
One major feature of the eZ8 programming model is
the lack of a fixed accumulator. Instead, any of the 4,096
possible RAM addresses can work as accumulators. The
CPU treats its main RAM (the file and SFRs — special
function registers — area) as a big set of CPU registers. In
order to accomplish that, RAM is split into register groups
(there are 256 groups of 16 working registers each). An
instruction usually works within a single working register
group, which is selected by an SFR named RP (register
pointer). Note that all SFRs are located at the last page of
RAM (addresses starting from 0xF00 up to 0xFFF).
Regarding the instruction set, there are 83 different
instructions split into two opcode pages. It comprises
usual instructions for basic operations such as addition,
subtraction, logical operations, data manipulation
instructions, shifting instructions, change-of-flow
instructions, some 16-bit instructions, bit testing and
manipulation, 8x8 multiply, etc.
The program memory area is organized so that the first
addresses are dedicated to special purposes. Addresses
0x0000 and 0x0001 are dedicated to the configuration
options; addresses 0x0002 and 0x0003 store the reset
vector; and so on. Table 1 shows program memory
0x0000 Option bytes
0x0002 Reset vector
0x0004 WDT vector
0x0006 Illegal instruction vector
0x0008 to 0x0037 Interrupt vectors
0x0038 to 0xFFFF User program memory area
Some devices also include a second
data space (up to 65,536 addresses) which
can only be accessed by using LDE/LDEI
instructions. This area can be used to store
less used data (as reading/writing to it is
slower than the RAM/SFR area).
The first implementation of FPz8 uses a very
conservative and hardwired design approach with two
main buses: one for program memory, and another for
register memory. As I chose not to include a data memory
area, the LDE/LDEI instructions are not implemented.
The program memory buses comprise a 16-bit
instruction address bus (IAB), an eight-bit instruction data
bus (IDB for reading data from program memory), an eight-bit instruction write data bus (IWDB for writing data to
program memory), and a PGM_WR signal which controls
writing to program memory. FPz8 includes 16,384 bytes of
program memory implemented using synchronous block
RAM (which means program memory content is lost when
the device is powered down).
The five register area buses comprise three for the file
register area (user RAM), and another two dedicated to
special function registers. There is a main 12-bit file register
address bus (FRAB), an eight-bit file register input data bus
(FRIDB), an eight-bit file register output data bus (FRODB),
an eight-bit register input data bus (RIDB), and finally an
eight-bit register output data bus (RODB) for writing into
SFRs. The FPz8 includes 2,048 bytes of user RAM memory
implemented using synchronous block RAM.
Figure 2 shows a block diagram of the FPz8; you can
see the CPU, two memory units (one for program storage
and the other for data storage), and also an external timer
Note that I am not using bidirectional buses for any
interconnects in this project. Unidirectional buses are
simpler to use, although they are less space efficient.
The VHDL description of the FPz8 is large and a bit
complex, so I am going to split its operation into some
modules to ease comprehension:
1. Instruction queueing engine
2. Instruction decoding
3. Interrupt processing
This article is focused on learning how a
microcontroller core is designed, and is intended
for educational use only. Please visit www.zilog.
com and check the manufacturer product line to
select a microcontroller that fits your project needs
(from eight-bit Z8 Encores! and eZ80 Acclaims to
the 32-bit ARM Cortex-M3 based ZNEO32! which
includes advanced motor control capabilities).
Table 1. Simplified program memory organization.
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