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such as z ≤a + b; is enough for a VHDL compiler to infer
the need for an adder circuit. This way, a designer can
focus on the task at hand rather than how to implement it
Here, you can see the power of an HDL based
approach to logic design; gone are gate and flip-flop level
logic designs, Karnaugh maps, and logic minimization.
Instead, one need only describe the pin-to-pin
functionality employing easy-to-use HDL statements.
Some of these statements are sequential; that is, they
signify operations that are performed one after the other.
Other statements are concurrent in nature, i.e., in the
hardware, they execute together at the same time.
architecture design of counter is
signal temp_clock : std_logic;
variable count : integer;
if (rising_edge(clock)) then
if count < 500 then
count := count + 1;
count := 0;
temp_clock <= not (temp_clock);
new_clock <= temp_clock;
Concurrent statements are a hallmark of HDLs; software
programming languages only have sequential statements.
HDLs need concurrent statements because — by their
nature — hardware works in parallel in real time, so their
descriptions require the ability to express simultaneous
circuit behaviors. Understanding concurrent versus
sequential statement execution is often the biggest
challenge in mastering HDL coding.
Getting Real with Code
Let’s look at some real code for configuring FPGAs.
The basics are logical (oh!) and not difficult to understand.
In VHDL, a digital system is described using two separate
but interlinked design units. The first (called an ‘entity’)
describes the desired system’s I/O interface; that is, all
signals coming in and going out of the system. This part
regards the system as a black box and pays no attention to
the function or structure of the system. That comes next in
the ‘architecture’ unit.
November 2017 25
FIGURE 1. Gate-level schematic; equivalent to a
typical conditional statement in an HDL.
This simple (and working) example shows VHDL code
for a clock divider that divides the frequency of a square
wave clock by a factor of 1,000. All VHDL reserved words
are in bold letters. This self-contained piece of code is
highlighted to show three main sections: compiler
directives; entity declaration; and architecture definition.
Let’s go over the code to see how everything is supposed
That is where you describe the system’s functionality.
That’s all. An entity architecture pair can be compiled by a
VHDL compiler to generate a circuit net list as a .sof file.
This is easier to show with an example:
entity counter is
port (clock : in std_logic;
new_clock : out
The first two lines make the VHDL compiler include
an IEEE standardized library with many essential definitions
for use in the compilation process. These lines are always
included in VHDL code that is fed to a compiler (note that
we never say VHDL or Verilog program). The next few
lines declare and define an entity that has been named
‘counter’ by the code writer. Any name (allowed by
identifier naming conventions) can be used.
In the entity part, you show the I/O of the system
within the keyword port. Here, two signals (clock and
new_clock) have been declared. The first signal enters the
system from the outside and is thus of the type (or in
VHDL parlance, mode) ‘in’ whereas the second signal goes
out of the system and is, therefore, of the mode ‘out.’
Any number of in and out signals can be included in
the port part. The mode can also be ‘inout,’ which stands
for a bidirectional signal. Here, the signals are std_logic
which essentially means they can represent a single bit
such as 0 or 1 (or even a high impedance state: Z). Multi-