X-Y BUFFER AMPS — In Figure 6, you
can see that the DAC0 (X axis) and DAC1 (Y
axis) signals from the Due are received and
buffered by high frequency op-amp U4.
Potentiometers are provided at this stage so
that signal gain (amplitude) and offset
(screen position) for X and Y can be
independently set. The gain pot on each
output will vary the amplitude within a 1.0V
to 4.0V P-P range. The centering pot varies
the signal offset so that it can reside
anywhere within a .2V to 4.75V window.
Final display adjustment will be a
combination of these AGI pots, as well as
the oscilloscope gain and centering controls;
my scope works well with AGI outputs
adjusted to 1.5V P-P centered about + 2. 5 VDC.
SAMPLE AND HOLD CIRCUITS — As seen in Figure 4,
the DAC0 and DAC1 outputs are not simultaneously output
by the Due CPU; the X value is converted first, followed by
the Y value one DMA_CLK cycle later. Analog switch U5a-b,
hold capacitors C9 and C13, and buffer amps U3a-b make
up the pair of Sample and Hold (S/H) circuits that align and
synchronize the X-Y point pair voltages, so they change
together when they’re sent to the oscilloscope for display.
The X and Y buffer amps are followed by transmission gates
U5a-b and output op-amps U7a-b which work together to
form two independent S/H circuits.
So, how do these S/H circuits work? Looking at the X
axis path, it shows that whenever transmission gate U5a is
turned on, the X axis voltage output of U4a is connected
to C12 and buffer amp U3a. When U5a is turned off, C12
stores (a.k.a., “remembers”) the voltage, holding the X axis
voltage stable even though the DAC output itself begins to
change in response to the next conversion cycle.
U5b, C10, and U3b perform the same S/H function
for the Y axis signal.
DATA CLOCK TIMING — COUNTER_TIMER_0 of the
Due is programmed to be the DMA_CLK. This signal
drives the internal DMA operations, but as shown in
Figure 7, also comes to the outside world through CPU
pin D2. This signal is fed to U6a and U8b to create all the
needed AGI timing signals. Flip-flop U6a divides the
DMA_CLK by 2 to create a signal that represents a point
pair transfer completed signal or POINT_CLK. The
POINT_CLK_NOT signal is then combined to generate the
S/H_PULSE and the SHOW_POINT signals. As depicted in
the timing traces of Figure 4, the S/H_PULSE signal is used
to “grab and hold” the X-Y voltage pair. Then, the
SHOW_POINT pulse is sent to the Z axis of the
oscilloscope (a.k.a., “Z-Drive”) to unblank each point after
it has settled down and is ready to be illuminated.
Build Note: Jumper PL6 is used to select the
“blanking polarity” and is set to match the blanking logic
used by our particular oscilloscope.
BLANKING SYNCHRONIZATION — It might seem a
bit unusual to see the analog output of DAC0 (X axis) also
connected and as a digital input to gate U8f. While this
looks a little weird, it’s a vital part of the X-Y axis signal
Introduction to Digital-Analog Conversion
DMA D/A Conversion with a SAM4S Microcontroller: The
27-Apr- 16 Robert Keim
Understanding & Using the SAM4S Digital-to-Analog
4-May- 16 Robert Keim
Digital-to-Analog Conversion with the SAM4S Peripheral
9-May- 16 Robert Keim
The Beauty of Brsenham's Algorithm
An Overview of Digital-to-Analog Converters and
Design Spark - Free PCB Layout Software
Arduino IDE, Source of Due Hardware, Arduino Libraries
AGI Hardware Details, Software Library, Sample
FIGURE 8. My first breadboard prototype.
February 2018 27