Nuts & Volts - May 2004

Your Next Digital Project

with the sync pulses to generate the display.

In order to generate a stable picture, the timing of the sync pulses must be exactly the same for each line. Being even one clock cycle off will cause a distorted picture. On the ATmega8, like most CPUs, an interrupt is not serviced until the current instruction is finished executing. Since some instructions take more cycles than others to complete, the interrupt response times vary.

To overcome this, the system timer actually generates two interrupts. The first interrupt occurs just prior to the timer reaching 63. 5 µs. System variables are saved and the CPU is placed into sleep mode. Shortly afterward, at exactly 63. 5 µs, the second interrupt calls the sync generation code. This method ensures that the interrupt response time is exactly the same and the sync pulses are identical.

Normal TV signals are interlaced pictures that use 525 scan lines per frame, refreshed 30 times per second. This display generates a non-interlaced picture. This format increases the refresh rate to 60 times per second, but uses only 262 scan lines per frame. This leaves a small blank space between each line. On smaller TVs, this is not noticeable; however, on larger TVs ( 25” and up), something similar to the display in Figure 3 might be observed.

About the Circuit

Now, let’s take a look at the schematic (Figure 4). The input port (J1) is connected to a 74HC573 octal latch (IC2). This holds the host’s input until the ATmega8 (IC1) can process it. The 74HC74 dual D flip-flop (IC4) has two functions. One flip-flop acts as the strobe latch and busy flag. It ensures that the host’s strobes are not missed by the ATMega8 during screen refresh. The second flip-flop

Main Program

Initialize program variables Read the NTSC/PAL pin Setup Timers for Interrupts Fill display RAM with a startup

Interrupt Service Routine

Update line counters Generate Sync Pulses

Active Display line?

No

Is the BUSY pin High?

No

Yes

Read host data byte Decode data byte Update Display memory

Clear the BUSY line

Read display characters Convert to font data Output to shift register

Return

Figure 2

Figure 3

divides the system’s 16 MHz clock in half to provide the proper shift rate (dot clock) to the shift register. The 74HC165 shift register (IC3) takes the parallel font data and shifts it out to the analog section. The analog section

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