A Really Solderless
by Al Williams
Last month, I showed you how easy it is to build logic
circuits using a Xilinx CPLD (Complex Programmable
Logic Device). This month, we'll dig into a more
sophisticated design. In particular, I'll show you how to
build a useful piece of test equipment — a "logic scope."
This is a poor man's logic analyzer. The logic scope reads
four bits of digital data, records them, and then displays
the waveforms on a normal oscilloscope (Figure 1).
This would be a formidable project if we were using
discrete gates and components. Of course, you could use
a microprocessor; however, it is difficult to make a
microprocessor sample at varying clock rates. Also, the
microprocessor must be able to clock much faster than
the incoming sample clock. Not only do you have to
observe the Nyquist limit, but you also have to have time to
execute many instructions before the next clock arrives.
The CPLD, on the other hand, can do all required
operations together on each clock. There aren't any steps
like those required by a microprocessor. With the logic
scope I've designed, you can feed in an external clock
from the system you are testing or an asynchronous
clock to make periodic measurements.
You can build the logic scope using the same
hardware you used for last month's adder project. That's
the beauty of a CPLD — you can reconfigure it to do
different tasks. I used the PBX- 84 prototype board (Figure
2) to build the circuit on a solderless breadboard. The only
unusual circuitry you need for the scope is a simple DAC,
made with common resistors (Figure 3). You can get fancy
and add some DIP switches and, except for the sake of
prototyping, you can use breadboard wires for the switches.
In addition to the five inputs (four data lines and a
clock), the scope also requires a four-bit trigger input and
a four-bit mask input. The logic adds the mask with the
incoming signal and compares it to the trigger. If there is a
match, the device starts storing data until its small memory
is full, then holds the buffer until the device is reset.
The connection to the oscilloscope requires four
outputs. Three outputs drive the DAC. You can think of
the two most significant bits as a "channel select," since
it sets the base level of the DAC for each of the four
channels. The least significant bit shows the state of the
channel (either 1 or 0). If you were to look at the output
normally, you'd see a staircase effect. To the left of the
screen would be channel 0, with channel 1 above and to
the right, followed by channel 2 a little higher and even
further to the right. Finally, channel 3 would be all the way
to the right and above all of the other signals.
That wouldn't be very useful, so the final logic scope
output provides a trigger that resets the scope trace for
each channel. Since the phosphor on the scope doesn't
go dark immediately and your eye retains the light, you
get the illusion of having four channels on a single scope
probe. Needless to say, PC-based or other scopes that
don't work like a traditional scope won't work for this
application. However, even a simple, one channel scope
will work, as long as it supports external triggering. If you
have a two channel scope, you can either trigger it
externally or on the second channel.
About Synchronous Logic
Figure 1. The logic scope in action.
NUTS & VOLTS
Unlike last month's project, the logic scope has a
wealth of flip flops and subassemblies made of flip flops.
Flip flops use a clock and allow you to store
data for later use. Using clocked — or
synchronous — logic also allows you to avoid
complex race conditions that are common
when trying to design asynchronous logic.
The basic type of flip flop is an SR (Set
Reset) flip flop. When you make the S
input true, the output goes true and stays
true, even if the S input goes false. The
output (conventionally called Q) goes false
when the R input is true and remains false
until another event on the S input occurs.
Of course, this presupposes that the S
Figure 2. The PBX- 84 board.