Nuts & Volts - May 2004

and R inputs won't be true at the same time. Another type of flip flop, —the JK — acts like an SR flip flop, but Q toggles if both inputs are true.

Sometimes, you want a flip flop that only toggles. For example, you might want to push a button once to enable a device (Q = true) and again to disable it (Q = false). You'll usually use a T flip flop for this type of circuit.

The final type of flip flop you'll commonly encounter is the D flip flop. This type of flip flop makes Q equal to the D input and holds that state. The advantage of clocked logic is that the flip flops only examine their inputs when they detect a clock edge. Even though different parts of the circuit might require different amounts of time to generate correct outputs, it will all work as long as no part requires more time than it takes to generate the next clock pulse.

This means, however, that it is vital for all flip flops to see the clock signal at the same time. If one flip flop sees the clock 100 nS before another flip flop, an incorrect operation may result (this is known as clock skew). To minimize this problem, CPLDs have unique clock pins that use special techniques to minimize skew. All of the flip flop clocks connect to one central clock.

This means you should avoid things like ripple counters, where one flip flop's Q output feeds another flip flop's clock. It is better to run everything off a single clock and use clock enable pins to enable or disable the clock, as necessary. For example, Figure 4 shows a simple, two bit ripple counter. Figure 5 shows how you can change this design to use a single clock. With this scheme, both flip flops get the same clock signal, but the lower flip flop only changes when the upper flip flop's Q is high.

It is very important to understand the components you'll use in a CPLD design. The Xilinx documentation discusses each block. Resets and presets require special attention. Sometimes they are synchronous and sometimes they are asynchronous. A synchronous reset has no effect if it occurs in between active clocks; however, an asynchronous reset will clear the output immediately. The chip has special global signals for resets, just as it does for clocks.

Figure 3. The DAC.

The Logic Scope

Figure 6 shows a block diagram of the logic scope. It has four major subsystems: Counter, Triggering, Storage, and Output.

The counter stage is a five-bit counter. It provides an address to the storage subsystem (three bits), plus an additional two bits to provide a channel to the output

MAY 2004

VCC

FTC

T

Q

Q0

CLK

C

CLR

FTC

T

Q

Q1

C

CLR

Figure 4. A simple two-bit counter with ripple clock.

subsystem. This allows the storage system to cycle through a complete channel (seven samples), then repeat the cycle for the other three channels in sequence.