Nuts & Volts - May 2004

A Really Solderless Breadboard — Part 2

VCC

FTCE

T

CE

C

Q

Q0

CLK

CLR

FTCE

T

CE

C

Q

Q1

CLR

Figure 5. A two-bit counter that uses clock enable.

and there is no previous trigger, the stage triggers the device. This resets the counter to zero and starts storing input data.

The storage system is simply a four bit by eight location RAM. Some CPLDs and FPGAs have RAM built into them, but the XC9500 does not. Still, it is easy to make RAM from spare flip flops. Another flip flop is set when the unit triggers and is reset when the counter wraps around. This flip flop controls the writing of the

memory. Therefore, the unit will only store input data during the first cycle after triggering. On subsequent cycles, the RAM only recalls its data.

The output system feeds the off chip DAC. It simply selects one bit from the storage system and outputs it to the least significant bit of the DAC. The two most significant bits are from the counter.

The DAC, incidentally, isn't very critical. I used all 22K resistors. The 11K resistors are actually two 22K resistors in parallel. The resistor network depends on the ratio of 2:1 resistance. The actual values are not that important, as long as the resistance isn't so low that the CPLD has trouble driving the DAC.

Implementation

You can see the top-level schematic for the scope in Figure 7. Notice that the RAM and the counter are both Verilog modules. The MASKCOMP module is another schematic (Figure 8). The M4_1E, FDRS and FD components are all standard components from the Xilinx library. The SEL(1) signal connects to the MSB of the DAC and SEL(0) connects to the middle bit. The LSB output connects to the LSB input of the DAC.

You can probably guess that the count3 component corresponds to the counter subsystem and the RAM 4 x 16 module is the storage system. I originally stored 16 slots instead of eight and never changed the name. The M4_1E component is the output selector.