The flip flops require a little
explanation. The FDRS flip flop in
the lower left corner controls the
writing of the memory. The other
FDRS flip flop controls the
triggered state of the unit. Notice
that there are a few low-level gates
to get all the logic straight.
The FD flip flop provides a one
clock cycle delay on the sync output.
Without this, the scope would
trigger before the counter resets to
zero and incorrect data will show at
the start of each sweep.
The MASKCOMP component is
a good example of how to divide
your circuit into subcircuits. It allows
you to test each component separately
and also makes higher level
schematics easier to understand.
Sometimes using a schematic
is cumbersome; for example,
consider the count3 component. It
is a five-bit counter with its outputs
partitioned into a three-bit sample
number and a two-bit channel number.
Sure, you can model this counter
with five flip flops, but the Verilog code is much simpler:
Figure 7. The top level schematic.
output [2:0] A;
reg [4:0] CT;
devise things, such as counters with a certain limit, large
dividers, or anything that would require a large number of
gates to represent in a schematic. Consider this Verilog
that defines the storage RAM:
/* 4x8 RAM (was 4x16 RAM) */
input [2:0] addr;
input [3:0] d;
output [3:0] q;
reg [3:0] mem [0:7];
always @(posedge clk)
if (rw) mem[addr]=d;
always @(posedge CLK)
The key to understanding this component is the
always block. On each rising clock edge, the component
increments the CT variable. The assign statements near
the top set various outputs to the different parts of the
variable. By using Verilog (or another HDL), it is easy to
This would be a substantial circuit to draw in the
schematic editor. Even if you did draw it as a schematic, it
would be tough to change the size, for example. In Verilog, it
would be a matter of changing the array subscripts to make
the RAM another size. In fact, you could use Verilog parameters
so that the sizes could easily be set by changing a single
parameter (like a C define) at the start of the module.
Verilog is a bit beyond the scope of this article;
however, these two examples should show you that it is worth
your time to learn it or a similar HDL. The Xilinx software
provides HDL templates for many common constructs, as well.
After you've implemented the design, you can ask the
Xilinx software for a timing report. This will tell you many