Multiplexing to Get More Outputs
Figure 2. Plot of data from Table 1. Address to resulting
outputs for an eight-bit multiplexer.
1 2 3 4 5 6 78
9 10 11 12
Figure 3. Possible number of outputs for four through 12 lines.
reasonable system that can be easily built and used, but will
also give us a good expanded output capability.
Circuit Building Blocks
low (all other seven outputs will be high).
Table 2 is a truth-table for the 74HC138, showing the
states of the outputs for all input combinations. The ‘-’ entries
are “don’t care” states. H is logic high or 5 volts. L is logic low
or 0 volts. Note that any enable input can disable the device.
The digital chips available that we will use to build up
our multiplexing output circuit are the 74HCnnn family of
chips, but similar functionality can be found in the other
74-series (74LS, for example) and also in the old 4000-
series CMOS devices.
For the address lines, we need to “fan out” the address
into N control lines. We’ll see why in a moment. The type of
device we want here is called a “decoder,” also referred to as
a “demultiplexer.” These take A address lines and produce
2A outputs, where one output as specified by the address is
at one logic level (typically Low) and all the other outputs
are at the other logic level (typically High). The two
most-used 74HCnnn devices for this are the 74HC138 (1-of-
8 decoder) and the 74HC154 (1-of- 16 decoder). The ‘138
(short for 74HC138) takes three address lines and produces
eight control lines, while the ‘154 takes four address lines
and produces 16 control lines. The
typical logic symbol for such a device
is shown in Figure 4.
The three address lines are A0, A1,
and A2. There are also three enable
lines that can be used to configure
multiple ‘138 devices to directly handle
up to six input addresses. To enable a
device, tie E1 and E2 low and E3
high. The eight generated outputs are
Y0 through Y7. The circles on the
diagram indicate that the active level
for that pin is inverted, thus we can
see that E1 and E2 should be low
(inverted), E3 should be high, and the
output addressed in Y0 to Y7 will be
For the data lines, we need to capture the data and
hold their values until we want them to change. The type
of device we want here is called a “latch” or a “flip-flop”
(FF). These devices take D data lines and will capture their
values when commanded to do so. The commonly used
74HCnnn devices for this are the 74HC74 (dual flip-flop,
two in one chip), 74HC173 (quad flip-flop, four in one
chip), 74HC174 (hex flip-flop, six in one chip), and the
74HC374 (octal flip-flop, eight in one chip).
These devices have data inputs, data outputs, a clock
input, and output enable inputs. The data on the inputs is
captured and presented at the outputs when the clock input
goes from a low to a high state. Tie the output enable(s) to
enable the device (low on the ‘374). Figure 5 shows the
typical logic-symbol for a 74HC374 eight-bit latch.
There is a device — the 74HC574 — that is identical in
Figure 4. Decoder logic symbol.
Figure 5. Eight-bit latch logic symbol.
OUTPUTS 0 - 7
TO ONE OF
‘138 W PINS