tions aimed at the ARM hardware
model. RDI is implemented by Segger
as an API (Application Programming
Interface) that is distributed as a
standard Windows DLL. Any RDI
compliant debugger can access the
services of Segger’s J-Link RDI DLL.
Up to this point, the LPC2136 and
its cousins have been presented as
super microcontrollers. Even with all
of that Flash and SRAM space
coupled with ultra high speeds, ARM
hardware only supports two hardware
breakpoints. This can present a
programmer efficiency problem as
some debuggers are designed to only
operate in SRAM.
Walking along a large amount of
code with only a couple of breakpoints
makes for a long debugging day. Most
microcontrollers have far more Flash
than SRAM. Thus, it may be difficult or
impossible for a standard SRAM-based debugger to load all of the
necessary program and data into the
SRAM area for debugging. The J-Link
RDI brings the LPC2136 and company
back to hero status by providing
unlimited breakpoint capability while
operating in Flash or RAM.
J-Link RDI’s ability to provide
unlimited breakpoints is made possible by the implementation of software
breakpoints. Hardware breakpoints do
not depend on code to operate as they
are part of the hardware architecture.
On the other hand, software breakpoints are implemented as minor
changes to the actual binary code.
A software breakpoint is created
when the debugger modifies the original program code at the desired
breakpoint location by replacing the
binary code at the breakpoint location
with a special breakpoint value. Thus,
multiple software breakpoints can be
placed at any instruction boundary
within the fabric of the binary code.
The firmware must be modified to
create a software breakpoint. So, it’s
obvious that software breakpoints are
most suitable to be placed within the
binary code that resides in SRAM.
To provide SRAM-like software
breakpoints in Flash, the J-Link RDI
software uses a small SRAM-based
application to reprogram a sector of
Flash that sets or clears a software
breakpoint in Flash memory. To
preserve the life of the LPC2136 Flash
memory cells, J-Link RDI only
programs Flash sectors when it is
absolutely necessary. Many times only
a single sector has to be programmed
as multiple software breakpoints are
often located in the same Flash sector.
Even though software breakpoints are being utilized, hardware
breakpoints are included in the
mix as well, when they can be used
efficiently by the J-Link RDI. A built-in
■ PHOTO 4. The first 64 bytes of code
you see in the Flash dump (address
0x0) make up the interrupt vector area.
This area of code is always remapped
to 0x00000000 thru 0x0000003F. We’ll
talk more about this code area later. The
LPC2136 SRAM begins at address
0x40000000 and I’ve used a bit of it as
a billboard in this shot. Note that
I dumped the SRAM in the J-Link
Commander window to prove a point.
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