BY ROBERT REED
• Totalize — One to 100,000 events
Although measuring pulse width
will lose accuracy below one microsecond due to resolution, it can capture and
display glitches down to 100 nanoseconds. Totalizing input pulses can be as
short as one microsecond or as long as
a month. All of the above functions will
accept any type of waveform.
Before we get into construction, I
will give a complete theory of operation
for understanding circuit operation and
eventual troubleshooting, if necessary,
upon completion. To aid in this discussion, I am including a timing diagram
which will be referred to in the schematic diagram. This will be of use because
there is a lot of high-speed sequential
edge triggering required in this unit.
The signal under test enters J1
and is amplified by Q1. R1 limits Q1
base current and C1 aids in high-frequency response. D1 clips negative
peaks to protect Q1. This stage has an
■ The display board.
overall gain of approximately three or
four. Its input sensitivity is 1.4 volts
peak, which is adequate for all logic
families in use today except ECL (0.8
vpp), but that’s beyond the intended
use for this design.
The input impedance is 22 kΩ,
shunted by less than 50 pF. This circuit
produced no noticeable degradation to
rise or fall times of the input signal. The
input can be of any waveform from 1.4
vp to 50 vp ( 100 vvp-p). Beyond 50V,
you will need an external attenuator.
This can be as simple as a resistance
divider if extreme speed is not an issue,
and it usually isn’t at these high levels.
The output of Q1 drives U1A — a
NAND gate with Schmidt-trigger action.
The output of U1A is a textbook-perfect
rectangular wave, no matter what wave
shape or amplitude is input to J1. Only
its length will vary, according to the
input signal. For this reason, I started
the timing diagram at this point.
The next stage — U2A — allows for
selection of positive or negative edge
triggering of the input signal while still
■ TIMING DIAGRAM
September 2006 47