operation will repeat itself. The reason
for this holdoff circuit is to latch the
count circuit into the display long
enough to read it. Without it, the digits would flicker constantly at higher
period rates. The holdoff time of 700
ms is arbitrary and may be changed by
adjusting the time constant of C5, R7.
At this point, we will switch from
analyzing signal flow through the front
end and focus on the time base. The
accuracy of any unit is that of its time
base and is given as:
Time base error in PPM,
± resolution, ± one display count.
■ A look at the internal wiring.
maintaining a positive-going pulse as
its output, since this is what the
circuitry that follows it wants to see.
The use of an exclusive OR gate fit
the bill perfectly here. A lookup of its
simple truth table will bear this out.
The output of U2A is split into
two paths: one to start the main gate,
F/F, and one to reset the same.
Assume for the moment that S2 is
switched to period mode of measurement; U3B will block any signals in
that path by grounding one of its
inputs. The leading edge of the pulse
applied to U3A is highly differentiated
by C2, R4. This will produce a 200
nanosecond positive pulse to U5A’s
clock input (P3). Only the leading
rising edges of the input will be seen
by this circuit, due to the gate configuration of U3B. U5A is a D type F/F
that is wired for toggle operation by
connecting P6 to the data input P2.
Now, starting from its reset position, Q (P5) will go high with the first
rising edge of the input pulse, low with
the next rising edge, and so on. This
produces a main gate pulse coincident
with the period of the signal under test.
Now, assume S2 is switched to
pulse measurement. U5A starts the
main gate action — output goes high
coincident with the rising edge of the
input signal. But now we have to
enable U3B by putting a high on one
of its inputs. U3C will
now perform exactly
as the above U3A did,
but with one exception — it will output a
200 nanosecond negative pulse only when
the input signal is on
its falling, trailing edge.
When U5A sees
this negative spike at
P1, it immediately
resets its output to a
low, and thereby aborts
its toggle operation.
Now the output at this
point is an exact replica
of the input pulse
width. Up to this point
at U5A P5, we have
an exact gating pulse based on either
period or pulse width and triggered
from either positive or negative edges.
Also from this point the gating
pulse diverges in three directions:
1. It enables main gate U6A for its
duration and allows selected master
clock pulses to pass through to the
counting circuits of U11A and U13.
2. It drives U7A to deliver the necessary timing pulses for latching and
resetting of the counters. U7A is a
leftover OR gate from a quad IC, and
is put to good use here as a buffer to
drive the high input capacitance
(1,000 pF) of the U1B circuit. Without
this buffer, some deterioration of the
main gate signal would occur.
3. Finally, it triggers U4A P5, which is
a dual monostable IC. Its role is that
of a holdoff circuit. As soon as we
complete one cycle of the main gate
pulse, the negative edge triggers P5
and produces a low at the P7 output
which disables U3A so that U5A
cannot operate again until the monostable times out (700 ms). This action
immediately blocks any input pulses
from entering U5A’s clock input and
keeps it that way. When the holdoff
times out, U3A is once again enabled
and will operate on the next incoming
signal pulse, at which time the whole
I decided to use a packaged
oscillator (eight-pin DIP) as it does
not cost much more than a lone
crystal — $1.70 for this unit. The
manufacturer guarantees ± 100 PPM,
but of the several units I purchased,
they were within 5 PPM at room
temperature. This accuracy is far
beyond what the display can resolve,
almost removing it from the equation.
Since we cannot escape the ±1 digit
in the display, accuracy depends almost
totally on resolution. The lower the
display count, the greater the possible
error. For example, with a display of 10,
due to resolution error, the actual count
could be closer to 9 or 11, a possible
error of 10 percent. This would be an
extreme case. The higher the count, the
greater the resolution, hence the greater
the accuracy. The only way to get
around this is to add more digits to the
display. I stopped at five digits, because I
felt I was at a point of diminishing
returns. I have checked this unit against
an expensive laboratory counter at full
display, and it was right on the money!
With that said, we will continue
with time base and master clock operation. XO is a 10 MHz oscillator ( 100 ns),
which is divided by 100 ( 10 μs), and by
100,000 ( 10 ms) through the divider
chain of U8, U9, U10. Three clock rates
can be input to U7bcd ( 10 MHz, 100
kHz, 100 Hz). The fourth input is 5
VDC for totalizing. Selection of these
inputs is accomplished by S4. Starting at
the top A position, 5 VDC is applied to
48
September 2006
