A Wide Range Period Counter/Totalizer
U6B gate, enabling the 10
MHz clock ( 100 ns) to pass
through U7 to the input
of U6A. Also Q2’s collector
is energized to light the
correct decimal point. At the
same time, a front panel LED
is lit through R14. This
would be labeled usec
and its count range will be
0-9999.9 μs.
With S4 switched to B
position, the U6c gate is
enabled, passing the
100,000 kHz ( 10 μs) clock
rate to U6A. Again, R15
lights the appropriate front
panel LED. Also Q3’s collector is energized, shifting
the decimal point. This is
labeled msec and its count
range is 0-999.99 ms.
With S4 in position C,
U6D is enabled, passing the
100 Hz ( 10 ms) clock rate
U6A. As before, R16 lights
the appropriate front panel
LED. The same decimal
point is lit as in B position.
Diodes D5 and D6 isolate
these switch positions from
inadvertently being energized from backfeeding.
This range is labeled sec and
its count range is 0-999.99 s.
Finally, with S4 in
position D, all clocks are
disabled, and a steady high
is applied to U6A. Now we
can count the actual gate
pulse as one digit per pulse
for a totalizing function.
Also, the manual rest line is
pulled low and kept there,
thereby enabling the counters to count and display
continuously without resetting and allowing totalizing
to occur. One word of caution here — S2 must be in
pulse mode when totalizing.
Now we are back to
where we left off on the
front-end circuitry at U6A.
When U6A P4 goes high,
the clock rate we have
■ SCHEMATIC 1
September 2006 49
