Nuts & Volts - September 2006

■ SCHEMATIC 2

selected will be present at U6A P5 input and passed through to the first counter U11A P1, which is a high-speed decade counter. Its overflow goes to U13, a multiplexed four-digit counter, latch, decoder. When main gate U6A P4 goes low, all counting stops and is stored in the counters. At this point, we have counted a known clock rate in an unknown gate time. When the count state is latched into the display, it will read out the gate time (our input signal under test) in real time.

For example, let’s say we had selected the S4A μs range and had counted and latched 5,000 clock pulses ( 10 MHz; 0.1 μs) during the time the main gate was enabled. The display would read 500.0 μs ( 5,000 times 0.1 μs). This is the period or pulse width from the circuit under test. Backing up just a bit, when U6A P4 went low, the first event to happen was that the counters stopped counting. The same main gate pulse was also coupled through U7A to U1B P12. U1B is a simple one-shot circuit, whose output is dependent on the RC time constant of R21, C8. In this case, it outputs a 15 μs positive pulse when triggered from the trailing negative edge of the main gate pulse. This pulse latches the count state into the display.