SOURCES
■ Silicon Laboratories ( www.silabs.com) — C8051F120;
C8051F120 Development Board
The following two lines of code take advantage of the
reset conditions of the XBR0, XBR1, and XBR2:
XBR2 = 0x40;
P1MDOUT |= 0x40;
// Enable crossbar and weak pull-ups
// enable P1.6 (LED) as push-pull output
■ Keil ( www.keil.com) — Keil uVison3 C Compiler
P3. What you would normally encounter with most other
microcontrollers here is a multiplexing scheme, which
allows predetermined system resources to share predetermined general-purpose I/O pins. The Digital Crossbar
approach allows all of the combinations of all functions. The
on-chip counter/timers, serial buses, HW interrupts, ADC
Start of Conversion inputs, comparator outputs, and other
digital signals in the controller can be configured to appear
on the C8051F120 general-purpose I/O pins specified in
the Crossbar Control registers.
I’m not going to insult your intelligence as I’m positive
that many — if not most — of you have configured and used
a microcontroller UART. Most of you are also already
familiar with how microcontroller timers operate. So, let’s
take command of the C8051F120 and all it has to offer.
TOOLING UP
When it comes to 8051 C compilers, you will have to
look hard to beat Keil’s uVision3 8051. The Keil 8051 C
compiler includes native support for the Silicon
Laboratories’ C8051F120. Just in case you’re wondering
why I didn’t go into excruciating detail about the
C8051F120’s internals and memory areas, Listing 1 shows
an excerpt from the C8051F120 include file (c8051f120.h)
that is part of the Keil 8051 C compiler.
It’s pretty obvious that the include file excerpt is a man-to-machine mapping of some of the C8051F120’s SFRs
(Special Function Registers). I purposely picked out the
Digital Crossbar definitions to give you an idea of how to
address the Digital Crossbar’s configuration registers. Let’s
walk through a very simple example of Digital Crossbar
configuration. Our goal is to enable general-purpose I/O
P1.6 as a push-pull output that will drive an LED. Push-pull
configuration of the general-purpose I/O port means that
when we write a logical 1 to the port pin, the output of the
port pin will go logically high. Conversely, a logical low I/O
instruction from the application will render a logical low at
the targeted general-purpose I/O pin output.
The bits contained within XBR0 enable or disable the
Comparator 0 output, the PCA0 module, UART0, SPI0, and
SMBus0. The corresponding bit in XBR0 must be set to
enable the peripheral represented by the bit. XBR0 resets with
all of its bits cleared. Thus, every internal peripheral represented in XBR0 is disabled on reset. We’re only interested in
defining a single push-pull output and none of the peripherals
represented by XBR0 need to be involved. XBR1’s bits deal
with interrupt inputs, among other things, and we don’t need
any of that right now, either. So, we leave XBR1 in its reset
state, which is all bits cleared and all corresponding services
represented by the bits disabled. I think you get the idea.
However, XBR2 houses the “weak pullup” bit, which is
enabled when the bit is clear. Thus, all we’re doing by
setting that single bit within XBR2 is to enable the Digital
Crossbar. Once the Digital Crossbar is enabled, we can set
the bit within the P1MDOUT SFR that configures general-purpose I/O pin P1.6 as a push-pull output. If we were to
hang an LED on general-purpose I/O P1.6 in a sourced configuration (LED cathode grounded), issuing an application
command to send a logical 1 to the P1.6 general-purpose
I/O pin would illuminate the LED.
The thing you want to take away from this is that
following a reset, you won’t have to worry about turning off
Digital Crossbar stuff you don’t need in your application. All
you have to do is enable the internal peripherals you intend
to use and turn on the Digital Crossbar if necessary.
NEXT TIME
LISTING 1
sfr P4MDOUT
sfr SPI0CKR
sfr P5MDOUT
sfr P6MDOUT
sfr P7MDOUT
sfr XBR0
sfr PCA0CPH5
sfr XBR1
sfr XBR2
sfr EIE1
= 0x9C;
= 0x9D;
= 0x9D;
= 0x9E;
= 0x9F;
= 0xE1;
= 0xE2;
= 0xE2;
= 0xE3;
= 0xE6;
Normally, we’re on the scent of assembling and coding
a particular application. Not so this time. So, we’ll explore
the capabilities of the C8051F120 using an off-the-shelf
Silicon Laboratories’ C8051F120 development board. That
will allow me to use the excellent Silicon Laboratories debug-ging/programming device in conjunction with Keil uVision3
to show you how things C8051F120 work at the bit level.
The C8051F120’s innards have been partially exposed.
We still have C8051F120 timers, UARTs, capture modules,
comparators, and such to work through physically and
logically. You will come to realize
that the ease of dealing with
the C8051F120’s Digital Crossbar
flows across all of the C8051F120’s
internal peripherals. The C8051F120
is a very powerful mixed-signal
SOC (System on a Chip). Just
because the C8051F120 is powerful
doesn’t mean it has to be difficult to
use. I’ll prove that to you in the
next installment of the Design
Cycle. NV
/* PORT 4 OUTPUT MODE */
/* SPI 0 CLOCK RATE CONTROL */
/* PORT 5 OUTPUT MODE */
/* PORT 6 OUTPUT MODE */
/* PORT 7 OUTPUT MODE */
/* CROSSBAR CONFIGURATION REGISTER 0 */
/* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
/* CROSSBAR CONFIGURATION REGISTER 1 */
/* CROSSBAR CONFIGURATION REGISTER 2 */
/* EXTERNAL INTERRUPT ENABLE 1 */
86
April 2007
