THE DESIGN CYCLE
Once the C8051F120’s Flash
memory system is set up for our
SYSCLK speed of 49 MHz, we can
activate the PLL (PLL0CN) and
configure the PLL filters for 49 MHz
operation (PLL0FLT). The PLL needs
some time to stabilize and when the
PLLCK bit (PLL0CN register bit 4)
transitions from low to high, the PLL
has locked into the desired frequency.
At this point, the C8051F120’s PLL is
the SYSCLK clock source.
■ FIGURE 4. This window
reminds me of that TV show
Let’s Make A Deal. There are
lots of knobs and switches
behind the “doors” in this shot.
ACTIVATING UART0
Okay, the stage is set for us to get
one of the C8051F120’s UARTs on
the air. Selecting the UART option
from the Peripheral pull-down menu
results in the display you see in Figure
4. In Figure 4, I’ve already performed
all of the UART configuration steps,
which explains why the UART0 is on
the Digital Crossbar, Timer 1 is the
baud clock source, and the baud rate
is set for 115200 bps. Although I’ve
greased the skids, we can still work
through the UART0 configuration
process together.
I went down the Configure Port
I/O path in Figure 4 to get to the
configuration screen shown in Figure
5. By selecting UART0, I attached
UART0’s transmit and receive pins to
the C8051F120’s general-purpose I/O
pins P0.0 and P0.1 respectively via the
Digital Crossbar. If you follow along
the Push-Pull / Open Drain general-purpose I/O status line in Figure 5,
you’ll see that I also configured the
UART0 transmit and receive pins as
push-pull. How did I know to do that?
I read the UART0 section of the
C8051F120 datasheet and followed
the rules that are laid down there. I
may not be the sharpest tool in the
shed, but I follow directions well.
Since we want to be able to make
our C8051F120 UART communicate
with a standard terminal emulator
running on a personal computer or
another RS-232 equipped device, I
selected standard eight-bit mode (see
UART Mode in Figure 4), which allows
us to use various standard baud rates
and provides for a start bit and one
stop bit in the asynchronous communications bit stream ( 10 bits total). No
rocket science here. The
baud clock for this mode of
UART operation can be provided by any of the available
C8051F120 timers.
However, the most
straight-forward baud clock
method uses Timer 1 in
Eight-Bit Timer/Counter Auto-Reload mode. As you can see
in Figure 4, I selected Timer 1
as the baud clock source. I
also disabled the baud clock
divider. The elimination of the
baud clock divisor (divide by
2) means that what we dial
in as a baud rate will be
calculated and applied as our actual
baud rate. Right now, we want to get
the UART0 transmitter up and have
no need to receive any data. So, I’m
ignoring anything that has to do with
setting up UART0 to receive.
Taking the Configure TX path in
Figure 4 opens the window shown in
Figure 6. As you can see, I’ve selected
the aforementioned Timer Mode
(Eight-Bit Timer/Counter Auto-Reload), identified the Timer 1 clock
source as SYSCLK, and enabled Timer
1. Our baud rate of choice is 115200
(I hope that’s okay with you) and I set
that up by clicking the Change Baud
Rate button you
see in Figure 6
and entering my
desired baud rate
for UART0. The
Configuration
Wizard 2 application determined
the reload value
for Timer 1 that
will supply a baud clock for 115200
bps. The reload value (0xE5) is loaded
into the high byte (TH1) register of
Timer 1 on every overflow of Timer 1.
A Timer 1 overflow occurs when
Timer 1 rolls over from all ones to
zero. The low byte register (TL1) is
always loaded with 0x00.
Lots of stuff happened while
configuring UART0. In the course of
putting together the bits and pieces
needed to spit bits from UART0’s transmit pin, Timer 1 was configured and
enabled. Here’s the UART0-related
Timer 1 code that the Configuration
Wizard 2 application generated for us:
■ FIGURE 5. In my
opinion, this is the
coolest window that
the Configuration
Wizard 2 application
offers. At a glance,
we can see all
of the C8051F120’s
general-purpose I/O
and peripheral configuration settings.
May 2007 83
