FIGURE 15. Ways of using two-input
NAND gates to make various AND and
NAND gates.
FIGURE 16. Simple three
input diode OR gate.
FIGURE 17. Six popular OR gate ICs.
Figures 18 and 19) are quad two-input
types; the 4075B and 74HC4075 (see
Figure 20) are triple three-input types;
and the 4072B (see Figure 21) is a
dual four-input type.
When using OR gate ICs, each
unwanted gate should be disabled by
shorting all of its inputs together and
tying them to one of the IC’s supply
lines. In CMOS ICs, the shorted inputs
can be wired directly to either supply
line, but in TTL ICs the inputs must
(to give minimum quiescent current
consumption with good
stablity) be tied high via a
1K resistor, as shown in
Figure 22.
Note that the fan-in of
a TTL NOR gate is directly
proportional to the number
of inputs used — at a fan-in
rate of one per input — and
that a TTL two-input OR
gate can be made to act as
a simple non-inverting
buffer by either tying one
input to ground or by tying
both inputs together,
as shown in Figure 23.
Just make sure the buffer
has a fan-in of one in
the former case, and a
fan-in of two in the latter.
Also note that OR gates
can be directly cascaded to
make a compound OR
gate with any desired
number of inputs. Figure
24, for example, shows
ways of cascading two-input elements to make OR gates with
three, four, or five inputs, and Figure
25 shows a three-input OR element
and a three-input diode OR gate
cascaded to make a compound five-input OR gate. NV
FIGURE 18. Functional diagram of the 74LS32
or 74HC32 quad two-input OR gate IC.
FIGURE 19. Functional diagram of the 4071B
quad two-input OR gate IC.
FIGURE 20. Functional diagram of the 4075B
or 74HC4075 triple three-input OR gate IC.
FIGURE 21. Functional diagram of the 4072B
dual four-input OR gate IC.
FIGURE 22. Method of disabling
a TTL OR gate.
details of the six most popular OR
gate ICs: the 74LS32, 74HC32, and
4071B (see
FIGURE 23.
Ways of using
a TTL OR gate
as a simple
buffer.
FIGURE 25. Example of a compound
five-input OR gate circuit.
FIGURE 24. Ways
of cascading
two-input OR
gates to get up
to five inputs.
70
June 2007
