Configuration Wizard 2 application.
Our goal is to write some C code to implement an
interrupt driven RS-232 communications engine using the
C8051F120’s UART0 as the central hardware component.
The first order of business is to allocate transmit and receive
buffer space within the C8051F120’s SRAM. Here’s the
code behind the buffer allocation:
// size of serial transmission buffer
#define TxBUFLEN 8
#define TxBUFMASK (TxBUFLEN - 1)
// transmission buffer start index
unsigned char TxHead;
// transmission buffer end index
unsigned char TxTail;
// storage for transmission buffer
char xdata TxBuf[TxBUFLEN]
// size of serial receiving buffer
#define RxBUFLEN 16
#define RxBUFMASK (RxBUFLEN -1)
// receiving buffer start index
unsigned char RxHead;
// receiving buffer end index
unsigned char RxTail;
// storage for receiving buffer
char xdata RxBuf[RxBUFLEN];
The transmit and receive buffers have a few things in
common. They both must be allocated in powers of 2. That
is, the least significant bit of the buffer length must always
be zero. Thus, the transmit and receive buffers are
allocated as 2, 4, 8, 16, 32, 64, 128, etc., bytes in length.
The reason for this is that we want the transmit and receive
buffer mask values to contain a 1 for every buffer location
except buffer location zero. For instance, our transmit
buffer length (TxBUFLEN) is equal to 8 which is 0b1000
(the 0b denotes binary just as 0x represents hexadecimal).
The transmit buffer mask value (TxBUFMASK) is derived by
subtracting 1 from the TxBUFLEN value, which results in a
TxBUFMASK value of 0b0111. Seven transmit buffer
locations are represented by 0b0111 with the zero transmit
buffer location representing the eighth transmit buffer
location. If we break down the creation of the receive
buffer mask (RxBUFMASK) value, we will end up with
0b1111, which touches the 15 receive buffer locations
following receive buffer location zero. You’ll get to see how
the transmit and receive buffer masks are used when we
examine the UART0
interrupt handler code.
As long as we keep
our transmit and
receive buffer lengths
below 256 bytes,
we can use eight-bit
character pointers to
delineate the transmit
and receive buffers’
beginning (Head) and
end (Tail). By incorporating the Head and Tail
in our buffer scheme, both of the transmit and receive
buffers can be considered to be circular. Incoming buffer
characters are stored in the buffer Tail address and outgoing
buffer characters are taken from the buffer Head address.
Thus, the Head is always chasing the Tail and the buffer is
considered empty when the Head address is equal to the
Tail address. Conversely, the buffer is full when the Tail
address is one less than the Head address.
To give you a better picture of the receive buffer
mechanics, I initialized all of the C8051F120 on-chip
peripherals, turned on the UART0 interrupts, and entered a
never-ending loop to capture 16 characters I sent from a
personal computer running Tera Term Pro. The results are
shown in the µVision3 Watch Window I captured for you in
Screen Shot 1. By declaring the buffer areas using
“char xdata,” both of the transmit and receive buffers are
allocated in the C8051F120’s on-chip 8K XRAM memory
area. Since the transmit and receive buffers are so small,
we could have also allocated them into the C8051F120’s
256-byte SRAM area using “char idata” in the buffer
declaration statements.
With the UART initialized to run in eight-bit mode with
its interrupts active and the transmit and receive buffers
allocated, our next step entails writing the receive interrupt
handler. No sweat. Coding the receive interrupt handler is a
walk in the park. Here’s the receive interrupt handler code:
static void com_isr (void) interrupt 4
{
// RECEIVE INTERRUPT HANDLER
unsigned char c;
if (RI0) {
c = SBUF0;
RI0 = 0;//read character
//clear interrupt request flag
//check for end of receive buffer
if (RxHead + RxBUFLEN != RxTail) {
//put character into buffer
RxBuf[RxTail++ & RxBUFMASK] = c;
}
}■ SCREEN SHOT 1. The 16 characters I keyed into the Tera
Term Pro window are shown in the hex dump area
beginning at address 0x00000 and ending at address
0x0000F. Note that the debug window points out the
beginning address (X:000000) of the receive buffer, which,
according to the “X:” is located in the C8051F120’s internal
XRAM memory.
June 2007 85
