FIGURE 7. An illustration of a logic analyzer’s display,
(somewhat simplified) so it remains uncluttered for
FIGURE 8. A time-correlated analog/digital view
of an anomaly.
acquisition memory full of data that can
be used to analyze the behavior of your
SUT in several different ways.
Analysis and Display
The data stored in the real-time
acquisition memory can be used in a
variety of display and analysis modes.
Once the information is stored within
the system, it can be viewed in formats ranging from timing waveforms
Figure 7) to instruction mnemonics
correlated to source code.
In newer systems with faster clock
edges and data rates, this is no longer
the case. As design margins decrease,
analog characteristics of digital signals
FIGURE 9. An illustration of how a
logic analyzer’s state acquisition
captures a “slice” of data across a
bus when the external clock signal
enables an acquisition.
increasingly affect the integrity of your
digital system. A time-correlated
analog-digital display using a logic
analyzer with an oscilloscope gives
you the ability to see the analog
characteristics of digital signals in
relation to complex digital events in
the circuit, so you can more easily find
the source of anomalies (see Figure 8.)
The listing display provides
state information in user-selectable
alphanumeric form. The data values in
the listing are developed from samples
captured from an entire bus and can
be represented in hexadecimal or
other formats. Imagine taking a
vertical “slice” through all the
waveforms on a bus (see Figure 9).
The slice through the four-bit bus
represents a sample that is stored in
the real-time acquisition memory.
Figure 9 shows the numbers in the
shaded slice are
what the logic
A display listing.
display, typically in hexadecimal form.
The intent of the listing display is
to show the state of the SUT. The
listing display in Figure 10 lets you see
the information flow exactly as the
SUT sees it as a stream of data words.
State data is displayed in several
formats. The real-time instruction trace
disassembles every bus transaction
and determines exactly which instructions were read across the bus. It
places the appropriate instruction
mnemonic, along with its associated
address, on the logic analyzer display.
Figure 11 is an example of a
real-time instruction trace display. An
additional display — the source code
debug display — makes your debug
work more efficient by correlating the
source code to the instruction trace
history. It provides instant visibility of
what’s actually going on when an
instruction executes. Figure 12 is a
source code display correlated to the
Figure 11 real-time instruction trace.
With the aid of processor-specific
support packages, you can display
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