■ FIGURE 3. Scope
discovered (the hard way!) that test probes can be a
hazard. To reduce the likelihood of shorting out power
circuits with a careless slip of the probe, the test points
are isolated with resistors (1K for low voltages and 10K
for high voltages). TP1 monitors the 5V DC output.
DC input power is from a 2.1 mm coaxial jack, CN1,
which mates to several commercially-made brick power
supplies. All other connections are made through CN2,
which can be a locking header (on the component side of
the PCB) to mate with a wiring harness or an SIP header
(on the solder side of the PCB) to allow the module to be
piggy-backed on another PCB, a 0.1 inch perfboard, or a
Generating a 200V main output along with a second
output of approximately 60V DC requires only one
flyback converter stage. This was accomplished by
tapping the inductor into “one third and two thirds”
sections so that the 60V output can be derived from the
tap. A commercial tapped inductor was not found, and
homemade ones worked well but are messy, so two
readily available inductors are used in series.
In any SMPS design, the components in the basic
loop (see sidebar again) are under a lot of stress.
Component types were carefully selected for the positions
of D2, D3, L1, L2, and Q3 — please do not substitute!
Ordinary rectifier diodes can’t be used for the HV
13. 3 280mA 3.72W
15,520 11. 86 mA
12.2 416mA 5.12W
15,520 13. 66 mA
■ TABLE 2. Measured performances.
outputs; the type specified is a fast recovery diode.
Most of the work is done by a DC-DC converter
control ASSP (Application Specific Standard Product), IC2.
The MC34063 has been on the market for a couple of
decades and is sourced by several vendors (and costs
less that one dollar in hobby quantities!). As the IC was
conceived in the days of power bipolar junction transistors
— which are current-driven switches — this circuit requires
another stage (Q1, Q2, R8, and R9) to drive the gate of a
modern voltage driven PMOS FET transistor.
The main output (HV1) is controlled by a feedback
loop that monitors the voltage developed on C7 and at
TP3 through a resistor divider chain (R3, R4, R5, and R6).
By making R5 a single turn potentiometer, the output
voltage can be adjusted over a 15% range. C3 is included
to improve stability, and the feedback resistor chain uses
two resistors (R3, R4) to limit the voltage stress on each
resistor (as I have found high value resistors to drift over
time under high voltage stress).
Internally, IC2 generates a 1.25V reference, and this is
compared to the voltage from the R5 wiper. Increased
output demand lowers the voltage on C7 and the voltage
at the wiper of R5, causing IC2 to increase the duration of
the drive pulses to Q3. With greater energy stored in the
inductor, the output rises to equilibrium again. When the
output load is reduced, the opposite action occurs.
Shorting or overloading the output is detected by the
current limit circuit and the output voltage is allowed to
Capacitor C4 controls timing of the internal ramp
generator in IC2 at about 35 kHz. I discovered that if the
voltage on this capacitor is taken slightly higher than
normal, the IC will shut down with no risk of damage to
it or other components. So, we have a simple way to shut
down the HV using a 5V (or greater) signal on CN2 pin 4.
C5 and R16 filter any noise from the control line.
When shut down, there is still a DC path through the
inductor and diodes to the outputs, so the lowest output
voltage is really that of the DC input supply (12V, in this
case), which is true of all inductor based flyback designs.
Output from IC2 is applied to Q1 and Q2 to ensure
that Q3 switches quickly and cleanly. Failure to turn Q3
on hard when the inductor is charging can lead to
overheating in Q3 due to I2R loss in the device. On
the other hand, not turning Q3 off quickly can cause
additional power loss in Q3. The parasitic capacitance
from drain to gate in Q3 can cause the FET to turn on
again mid cycle, usually with destruction of the device!
Unused energy from the inductor
P Out Eff oscillates with stray capacitance
and Q3 drain, causing ringing (see
2.18W 58% Figure 3).
Q2 clamps the gate to near
ground during the off cycle, and
Q1 sources current into the gate
capacitance during the on cycle.
Q3 lives a hard life with both high
(Using Digi-Key T983-P5P-ND DC supply or equivalent.