ADVANCED TECHNIQUES FOR DESIGN ENGINEERS
■ BY FRED EADY
UP THE LOGIC FOOD CHAIN
I was a totally analog teenager. My interests then were centered on tube-based
stereo equipment and tube-based guitar amplifiers. I was fat, dumb, and happily
analog until I ran across a copy of the GE Transistor manual in the literature
section of a local electronics parts store. I had to have it. Everything “electronic”
I was reading about at the time was telling me that vacuum tubes were on
their way out and transistors were the thing of the future. At that time,
hand-held calculators were becoming popular and as far as I was concerned,
they were “magical” devices that I would never ever understand at the
electronic level. So, in an attempt to embrace transistor technology, everything
“tube” was replaced with a comparable “transistor” device.
My guitar amp and stereo projects became
transistorized. I even started to wonder about what
was inside of those “magical” calculators. As I transitioned
from teen to adult, building stereo equipment and guitar
amps gave way to transistor and IC-based logic projects.
The transition was complete. Well, not quite.
These days, my guitar amplifiers are all tube-based.
However, I’m still “solid-state” when it comes to logic. In
past Design Cycle columns, we’ve explored the nuances
of many a microcontroller. We have also recently delved
into the world of CPLDs. It’s time to move up another step
on the logic food chain. In this installment of Design
Cycle, we are going to tackle the FPGA.
FPGA is short for Field Programmable Gate Array.
In reality, an FPGA is actually a programmable solderless
breadboard populated with interconnectable logic blocks.
An FPGA differs from a CPLD (Complex Programmable
Logic Device) in that the FPGA contains
considerably more logic gates. Also, an
FPGA may contain memory and high-level
embedded building blocks such as adders
CPLD logic is based on sum-of-product
logic arrays that interconnect and feed
■ FIGURE 1. If we choose to use the D flip-flop
output, the output of this LUT is registered.
Bypassing the D flip-flop all together results
in an unregistered output signal.
clocked registers. FPGA logic is rooted in LUTs (Look-Up
Tables) such as the one you see in Figure 1. Basically,
we can configure the LUT to be any type of logic gate
with up to four inputs. The clock signal in Figure 1 would
normally be provided by the FPGA’s internal clock
routing system. Depending on our desired logical
function, the LUT infrastructure allows us to pass our logic
output through the D flip-flop for registered operation
or bypass the D flip-flop for an unregistered output
The power of the LUT comes in numbers. The FPGA
fabric allows for interconnection of a large number of
LUTs. Using the FPGA’s internal interconnection fabric
allows us to combine the logic contained within a large
number of LUTs to generate complex logical operations.
In this spin of Design Cycle, we will be basing our
FPGA designs on Xilinx FPGAs. Thus, the generic concept
of a LUT is similar to what Xilinx calls a CLB (Configurable
Logic Block). A CLB is made up of function generators,
registers, and reprogrammable routing controls. Equating a
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