THE DESIGN CYCLE
voltage regulator. In addition, vias and
any other indirect means of connecting
the output capacitors to the LP3872
output pin is taboo. You can see how
I followed the rules by examining the
printed circuit board (PCB) top copper
layout of the voltage regulators
and their associated capacitors in
Screenshot 1. All of the voltage
regulator input and output capacitor
hardware interconnects are large
direct copper paths that tie directly
to the pins of their associated voltage
regulators. I also carried the LP3872
PCB layout rules over to the LP38855 circuitry.
Vias are only used to transfer the output voltages
to the internal voltage planes within the four-layer
ExpressPCB printed circuit board. I’ve isolated the three
PCB power planes in Screenshot 2. Note that I positioned
each quad of voltage regulator output vias to feed their
respective power plane partitions. The silkscreen in
Screenshot 3 zeroes in on the locations of the vias that
are feeding the XC3S50A power pins. A total of four
VCCINT pins are fed from the power plane partition and
are marked with an “I.” There are also four VCCAUX
power inputs. You can get an idea of where they are as
they are marked with an “A.” All of the XC3S50A I/O
banks are powered by the VCCO partition. There are two
power inputs per bank. I’ve identified the VCCO power
points with numbers that represent the banks (00,01,02,03)
that are being fed by vias located within that power
partition.
The voltage regulators are all fed from a common 5.0
volt source. I used a regulated wall wart to supply the bulk
5.0 volts. There are a couple of reasons I chose to drive
the XC3S50A power supply with 5.0 volts. Some
peripherals that I would like to drive with its require a
■ SCREENSHOT 3. The large dots are
ground plane connections and are “no
connects” to the power plane. There
are smaller dots next to each of the
silkscreen legends that are, in reality,
the vias that are taking power from the
planes to the XC3S50A power pins.
5.0 volt power rail. One good example
of this peripheral is an industry
standard 16 x 1 LCD module. The
other reason I selected a bulk input
voltage of 5.0 volts is that the
LP38855 can only tolerate up to
5. 5 volts on its input. I decided to
exclude the 5.0 volt bulk input voltage from the PCB
power plane. Instead, I designed in a 5.0 volt header
next to the solderless breadboard that I feed with a trace
on the solder side of the PCB.
The XC3S50A power supply voltage regulator
components come together as shown in Photo 2. As
you can see in this photo, the 3. 3 volt LP3872 voltage
regulators are also packaged in a TO-263 form factor
and are specified as LP3872ES- 3. 3. No logic power supply
system is complete without power bypass capacitors. I
mounted the 0603 FPGA bypass capacitors on the solder
side of the PCB (as shown in Photo 3) to keep things tidy
on the component side of the PCB. The XC3S50A power
supply bypass capacitors and their associated power pins
are broken out for you in Schematic 2.
PROGRAMMING THE XC3S50A
I introduced you to the Xilinx platform cable USB
programming device when we were adding CPLD devices
to your Design Cycle. I also used this programming device
for our foray into FPGAs. We will use the platform cable
USB again to drop code into our 50A design. To gain
access to the services of the platform cable USB, all
■ PHOTO 2. Using these LDO voltage regulators only required a
couple of extra solder joints each. We have the space, so I
designed in the large tantalums. In a space-constrained application,
we can ditch the big caps and go with the smaller ceramics.
■ PHOTO 3. These 0603 .1 μF capacitors are tiny.
However, I managed to tie them all down using a
standard soldering iron.
September 2008 69
