■ PHOTO 7. All of the lessons learned from the XC2C64A
CPLD development board project have been incorporated
into the development board you see here.
COMPLETING THE XC3S50A
HARDWARE DESIGN
I couldn’t decide which clock frequency would work
best. So, instead of designing in a permanent clock
oscillator, I decided to include a four-pin socket to
accommodate 3. 3 volt, half-sized clock oscillator modules.
The Jameco ( www.jameco.com) solderless
breadboard module worked out very well in the XC2C64A
CPLD design, so I have included it in our XC3S50A
design. I also pulled the CPLD LED bank into our FPGA
design. Another point that proved itself in the CPLD
design was the use of female interconnect points. As you
can see in Photo 7, I have used female I/O connectors
exclusively in this design.
Rather than try to cram every conceivable peripheral
onto this development board, I added six 2 x 6 I/O
peripheral portals. Each right-angle 2 x 6 female interface
is directly wired to a companion 2 x 6 straight-up female
connector. The beauty of these I/O portals is that they
are compatible with a series of prefabricated I/O modules
that are available from Digilent. The Digilent I/O module
series includes seven-segment LED displays, H-bridges,
pushbutton arrays, slide switch arrays, RS-232 interfaces,
and LCD modules. In many cases, pictures speak louder
than words. So, let’s work on putting the Digilent LCD
module you see in Photo 8 to work.
FPGA TO LCD
The PmodCLP LCD module is unique in that it
operates at 3. 3 volts. An on-board boost voltage converter
hops up the incoming 3. 3 volts to 5.0 volts needed by
the LCD electronics. Thus, it is very easy to interface the
PmodCLP module’s power, data bus, and control signals
into our 3. 3 volt XC3S50A system.
72 September 2008
■ PHOTO 8. I designed the XC3S50A development board’s
I/O ports to accept the six-pin footprint of the Digilent series
of prefabricated I/O modules. Most of the Digilent I/O modules
sport single-row interfaces. The LCD module in this shot has
both single-row and double-row six-pin I/O interfaces. You
can also easily see the relationship between the right-angle
and straight-up 2 x 6 connectors in this view.
The PmodCLP J1 connector is not divided into odd
and even rows as one would expect. I discovered this when
the FPGA power supply shut down when I plugged the
PmodCLP into the sockets I had wired into the FPGA. Instead,
count from J1 pin 1 along the same row to J1 pin 6. J1 pin
7 is positioned relative to J1 pin 1 and you count down
the J1 pin 7 row to J1 pin 12. I’ve included a schematic of
the PmodCLP in the FPGA download package, which you
can get on the Nuts & Volts website ( www.nutsvolts.com).
All of the PmodCLP’s data I/O lines are terminated on
its J1 pins. The PmodCLP’s J2 pins transfer the PmodCLP’s
E (Enable), RS (Register Select), and R/W (Read/Write)
LCD control signals. Power for the PmodCLP can be
applied to power pins within the J1 or J2 connectors.
I can best show you how the PmodCLP hardware
connects and operates by showing you the Verilog code.
So, let’s start from the top of the Verilog LCD driver code
and work our way down:
module lcd_drvr(
input clk_10mhz,
input reset,
output reg lcd_e,
output reg lcd_rs,
output reg [7:0] lcd_data,
output reg [7:0] led_out
);Hopefully, the module definition code snippet looks
familiar. Our input clock frequency is 10.0 MHz. The input
clock is tied by PCB trace to pin P124 of our XC3S50A. The
active-low reset input connects to pin P33 of the FPGA. We’ll
use the reset input as a firmware reset to make sure that all
of our LCD driver variables are initialized to our predetermined
states. With the exception of the led_out output register,
the rest of the registered outputs are associated with the
