Nuts and Volts - February 2009

■ FIGURE 1. Baseboard-2 schematic.

has your registration ID. You might want to cut and paste this ID into a file for use in the installation, and in case you want to reinstall the package. This page also has several links for documentation and two links for downloading WebPACK. It is probably best not to click the large Download button as this tries to install software on your PC. Instead, select the "Download Files Individually" link, and then select the Download link which appears next to the file size. The 2.2 GB download is going to take awhile even on a relatively fast Internet link.

The WebPACK download file is in a "tar" format, which — while common on Linux — is not well known on Windows. Windows users

may need to install a package such as WinZip ( www.winzip.com) or WinRAR ( www.winrar.com), both of which can handle tar files.

Install the software by double-clicking setup.exe in the ZIP file or (for Linux) by untarring the download file and running the "setup" script in the top level directory. Windows users will need administrator privileges to install the software. The default installation directory on Windows is C:\Xilinx\10.1 and on Linux it is /opt/Xilinx/10.1. If installing on Linux as a non-root user, you might want to create /opt/Xilinx/10.1 beforehand and give yourself write permission on it.

The installation will ask if you want to do an immediate update and whether or not to install the cable drivers. Saying "yes" to an immediate update is a good idea but will trigger another 600 MB download. For this tutorial, you do not need the update and can safely postpone it. You can also say "no" to the "Install Cable Drivers" option since the board we're using does not need JTAG drivers. The installation takes 10 to 20 minutes once all the licenses are accepted and the installation options are set. Test the installation on Windows by opening a Command window and entering the command:

Creating a Simple Counter in Verilog

C:\Xilinx\10.1\ISE\ bin\nt\xst -h.

On Linux, the command is:

/opt/Xilinx/10.1/ISE/bin/lin/xst -h.

■ LISTING 1. A User Constraints File for the Baseboard-2.

If everything is installed correctly, you should see a display of the usage of the xst command.

From this point on, I won't give the full path to the command. You should either prepend the full path to the command or modify your shell's execution path variable. A convenient way to do this on Linux is to source /opt/Xilinx/10.1/ ISE/ settings32.sh.

The Xilinx tools can compile either Verilog or VHDL and I've chosen Verilog for the test program. Whether it’s VHDL or Verilog, you have to tell the compiler about the hardware on your FPGA board. The Xilinx "User Constraints File" contains these definitions. Figure 1 relates FPGA pin numbers or locations to logical names for use in the Verilog code. Consider, for example, this partial schematic of the Demand Peripherals Baseboard-2. The constraints file for this hardware might look like that shown in Listing 1. The NET field is the pin name as it appears in your Verilog program. The LOC field is the pin location on the physical FPGA. Xilinx specifies pin locations as the letter P, followed by the pin number on quad-flat packs, and by the grid location for parts in a ball grid array package.

The user constraints file can do much more than just relate Verilog names to pin numbers. It can also add pull-up or pull-down resistors, set output current limits, set timing constraints, and set output slew rate. Details about the user constraints file can be found on the Xilinx website by searching for "user constraints file." In particular, additional information is available in this document:

http://toolbox.xilinx.com/docsan/ data/alliance/dev/ dev3.htm.

Use Notepad, vi, or your favorite editor to create a text file named counter.ucf and copy Listing 1 into it. (All three files for this article are available in the download section of the Nuts & Volts website (

www.nuts volts.com).

The Verilog program for this tutorial implements a simple counter that counts an input clock and displays the high eight bits on the LEDs. A clear input can force the count to zero. Figure 2 illustrates the circuit for the Verilog design shown in Listing 2.