Nuts and Volts - February 2009

>>>READER-TO-READER QUESTIONS AND ANSWERS

unless you need repeatability for manufacturing purposes. This circuit is based on proven designs, but has not been tested as drawn. Add power supply bypass caps, and read the LM111 datasheet if things don't go well in the lab.

Mike Hardwick Decade Engineering

[#1095 - January 2009]

One Minute (or More) Timer

I need a way to reliably trigger a 555 from a loss of input signal. I've tried several schemes involving capacitor discharge when the input disappears but they have not proven to be reliable. Keeping the input high apparently doesn't let the device time out, so it needs to be a positive-going pulse.

#¹ Well, my first thought was to hark back to an article here in N&V a while back where it was noted that a certain PIC was cheaper than a 555 timer chip(!), and thinking "Well, shucks, get a cheap PIC and program it up to do what you want."

If that's too intense or you want a purely non-computer solution, then you need a 'signal conditioning circuit' prior to your 555. In this case, this may be as simple as a capacitively-coupled input circuit (a simple RC circuit that I don't think I'd better try to draw with ASCII graphics). You indicate that you've had some trouble with reliability with capacitor discharge circuits — what you want is capacitor INPUT, not discharge.

However, it may be easier to rig up some sort of one-shot circuit, using either a 'one-shot' IC, or use an inverter chip (usually with six or eight inverters), using some of the inverters as delay elements. So, you would wire three, four, or more inverters

(or buffers) as sort of a delay line (above) to feed a delayed signal to the last gate, which is drawn in my figure as a box, but which should be either an xor or perhaps a nand. The idea here is that there is a short time (n gate delays) where the inputs will be different. Depending upon whether you need a positive or a negative pulse upon trigger (and the polarity of your trigger, AND whether you use buffers — as I drew — or inverters), you may need a NAND, an XOR, an XNR, or an AND gate (Note: an AND gate is just a NAND with an inverter following, if you don't happen to have an AND handy). Finally, if the pulse isn't long enough after using all the gates, you can insert some more delay by using capacitors and resistors to slow down the rise (or fall) times of the signals passing through your delay line.

Rusty Carruth

#²Since your design is only working to a certain degree, there are probably some issues with the design itself (an LM555 was assumed).

1. Inadequate power supply

bypassing is highly likely; 1 μF electrolytic parallel with 0.1 μF ceramic is recommended and required since the totem pole output has serious current spikes. Keep in mind that the output can source and sink a very high 200 mA. Use high quality components designed for this application.

2. Unused inputs need to be tied to a defined state. The reset input must be tied to Vcc if not used to avoid false triggering.

3. The switch point for the trigger input is 1/3 Vcc. This usually requires a stabilized supply voltage. Use a three-legged regulator.

4. Keep in mind that all capacitors suffer from dielectric absorption (also called dielectric soakage or dielectric memory), an effect which manifests itself when a recently charged and then discharged capacitor bounces back as observed on a high input resistance meter. Teflon, polystyrene, polypropylene are reasonably good, but aluminum and tantalum are really bad choices as dielectric.