■ FIGURE 6. Divide-by- 10 Implemented with Transistors.
meaning the divide-by-six counter drives one of six lines;
the decade counter drives one of 10 lines; and the hours
counter drives one of 12 lines. For each numeric display,
the decoded lines drive a diode array that implements a
wired OR function. Figures 7 and
8 show the seven-segment decoder in action.
60 Hz Extraction
This clock uses the 60 Hz signal from the power
company as a time base. Unfortunately, the power signal
■ FIGURE 7. Seven-Segment Decoder.
■ FIGURE 8. Seven-Segment Decoder.
has spikes on it from equipment switching on and off, and
these spikes can trigger the counters and falsely advance
the time if allowed to propagate to the counters. Previous
attempts to place an analog RC low pass filter on the
60 Hz did not prevent all power spikes from erroneously
advancing the time. I devised a “brick wall” low pass filter
with a cutoff at about 100 Hz. The logic is shown in
Figure 9 and the transistor implantation is in Figure 10.
In short, the 60 Hz sine wave is squared up, a pulse
is developed from one edge, the pulse discharges a
capacitor which charges up at a calculated rate, and the
capacitor voltage is level compared
to produce 60 Hz. The point of all
this complicated rigmarole is that
when a noise spike causes an extra
pulse, it merely discharges the
capacitor and causes a delayed
edge on the output of 60 Hz so
that the noise affects the duty
cycle, not the frequency. It would
be possible that a long noise burst
could remove one cycle, but that
rare likelihood has the almost unnoticeable effect of losing 1/60th of a
second. The transistor implantation
in Figure 10 shows two four-