Nuts and Volts - May 2010

type has phase error that is proportional to the frequency difference and is useful as a frequency discriminator. The LM565 is an example of a type 1 PLL and is covered in detail in National Semiconductor Application Note #46. The application note is heavy on math, so I will try to boil it down to the essentials.

A logic XOR can be a phase detector (mixer). When both inputs are in phase, the output is low; when both inputs are 180 degrees out of phase, the output is high. The DC output after filtering is proportional to the phase angle, being 50% at 90 degrees. Although it is not obvious, the voltage controlled oscillator (VCO) is a phase integrator. When there is a frequency difference between the input signal and the VCO, the phase difference just keeps accumulating. Since the filter at the phase detector output has 90 degrees phase shift above the cutoff frequency, and since the VCO is an integrator which has 90 degrees phase shift, the closed loop will oscillate if there is positive gain at frequencies above the low pass filter cutoff. One solution is to reduce the open loop gain, but that impacts the ability of the loop to follow frequency changes.

For a high performance loop, it will be necessary to put in a phase lead at F2 which is accomplished by a resistor in series with the filter capacitor; F2 = 1/( 2*PI*R2*C1) — see Figure 3. The low pass filter rolls off at 6 dB per octave and the VCO rolls off at 6 dB per octave for a total of 12 dB per octave at frequencies above the filter cutoff. The filter cutoff (F1) is: F1 = 1/( 2*PI*R1*C1).

An American engineer, Hendrik Bode, discovered that the closed loop can be stable if the open loop is rolling off at 6 dB per octave as it goes through 0 dB. Stability is not guaranteed but improves with a wider frequency range of 6 dB rollof. The closed loop bandwidth of the PLL is determined by the 0 dB intercept of the open loop gain.

■ FIGURE 5

■ FIGURE 3

low pass filter is too close to the oscillator frequency for effective filtering, then move F1 to a lower frequency (much lower) so you can install a phase lead at F2 that is below the new F0 such that the plot passes through 0 dB at 20 dB per decade. See the dashed line in Figure 4.

By following these rules, you should be able to design a PLL with the stability and bandwidth you want.

CLOCK OSCILLATOR SCHEMATIC

QI have an old sound chip that needs a clock source. Unlike a modern chip that I’m used to, it doesn’t have two pins I can straddle a crystal across — rather it has only a single pin. How can I generate a (roughly) 2 MHz clock signal to drive this chip?