Nuts and Volts - November 2010

connect the top and bottom ground planes at the PIC18F46J50’s VSS pins. Pin 3 of the ICSP portal is also a thermal ground feed through. Three other thermal feed through ground pads can be found at the pair of GND pads and the ground pin of the external power source connector. Good examples of feed through vias can be seen at the tab of the TC1262-3.3 voltage regulator. Feed through vias are placed everywhere a ground connection may be pinched off on the top-side ground plane. In all cases, the bottom ground plane uses the feed through vias to provide a ground path to the isolated top plane area. You can explore the various feed through vias, component connects, and thermal pads by altering the views of the ExpressPCB files in the download package and comparing the physical attributes of the PIC18F46J50 daughterboard to the graphics of Schematic 1.

Our universal design becomes truly universal when it is mated to external devices. To insure the success of that merger, all of the PIC18F46J50’s header pads, the ICSP pads, the pair of thermal GND pads, and the external power input pads are all on 0.1 inch centers. A fully populated daughterboard is the focus of Photo 2.

BUILDING AN EDTP MICROSD INTERFACE CARD

When I got the hots to do this project, I just couldn’t wait for a PCB. So, I threw together the microSD card contraption you see in Photo 3. Although it seems to be solidly constructed in the photograph, it took a couple of microSD card sockets and a couple of hours to get it all to stick together. That was enough to slap me back into reality.

The trace elements of the microSD interface card are routed in Screenshot 5. Pins 1 and 8 are not used in SPI mode. So, to keep this PCB as small as possible, there are no header connections for the unused pins.

Clicking on the microSD interface card components will tell a story that confirms the story being told by Schematic 1. A pair of pull-up resistors and a pair of power supply bypass capacitors support the microSD card socket and a tristate buffer. The MC74VHC1GT125DT tristate buffer isolates the microSD card’s output which allows other SPI devices to be serviced from the host’s SPI portal.

The interface card headers are labeled from the microSD card perspective. SDO — which is Microchip for MISO (Master In Slave Out) — connects to the PIC18F46J50’s SDI pin. SDI is Microchip for Master Out Slave In (MOSI) and connects to the PIC18F46J50’s SDO pin. The PIC18F46J50 is the SPI master device and provides the clock which emanates from the PIC18F46J50’s CLK pin. The microSD card and the tristate buffer outputs are activated with a low-going logic level on the CS pin. The header silkscreen legends are visible in Screenshot 6.

■ PHOTO 4. This is a bit prettier than the lashup in Photo 3

and much easier to assemble and use.

DESIGN CYCLE

■ PHOTO 2. It’s all here except the header pins.

The same ground plane logic we used on the daughterboard is extended to the microSD card interface design. Note the thermal feed through at the GND pin and the top-side ground plane component connections in Screenshot 7. The assembled EDTP microSD interface card you see in Photo 4 measures in at 0.675 x 1.10 inches.

■ PHOTO 3. Not only is this ugly, it’s hard work.

LOADING THE BOAT

As I mentioned earlier, we’re probably going to need an extra board or two to tie everything into a useful design. In that the microSD interface card headers won’t directly line up with the PIC18F46J50 daughterboard headers, we’re going to need to add a motherboard to provide a means to make the necessary connections.