Nuts and Volts - September 2011

www.nutsvolts.com/index.php?/magazine/article/september2011_DesignCycle

DESIGN CYCLE

■ PHOTO 2. An FT232RQ and a HVC241 gate IC are mounted on the other side. We built a garage-brewed version of this debugger/programmer in the September ‘ 10 edition of Design Cycle.

vos_iomux_define_output(40,
IOMUX_OUT_GPIO_PORT_A_1); // LED2#
// GPIO Port A 2 to pin 41 as Output.

The IOMUX configuration code can be manually created or we can go the easy way and have the Vinculum-II IDE’s VNC2 IOMux config utility generate the code for us. The config utility is part of the Vinculum-II IDE and is easy to use. So, with the help of the utility, I’ve selected and configured the Vinculum-II’s pin 39 in Screenshot 1. The same procedure was performed for pin 40. Note that in the pin 40 configuration I chose to use the next available PORT A I/O position (A1). The Vinculum-II architecture requires us to create an instance of the GPIO context, whose template — gpio_context_t — is located in the API file GPIO.h. The context template is a simple structure that is commonly used in C programming:

// GPIO context
typedef struct _gpio_context_t {

 unsigned char port_identifier;
} gpio_context_t;

We’ll call our newly created instance of the GPIO context gpioCtxA. Again, we’ll use standard C methods to instantiate the new context:

gpio_context_t gpioCtxA;

Now that we have generated a unique context for our IOMUX definitions, we need to associate our PORTA I/O definitions with the Vinculum-II’s physical PORTA device

3V3

C15 100nF C16 100nF C17 100nF C18 100nF R4 360

R5 360

R13 360

3V3

■ SCHEMATIC 1.

There's no Vinculum-II rocket science here. This is a standard Vinculum-II setup.

LED1

GRN LED2

3V3

R2

10K R1 10K IO15 IO1

2 21

38 54

3. 3 VREG IN VCCIO 3.3V

VCCIO 3.3V VCCIO 3.3V

37 41 42 43 44 45 46 47 48 49 50 51 52 55 56 57 58 59 60 61 62 63 64

USB2DM IO BUS22

IO BUS23

IO BUS24

IO BUS25

IO BUS26

IO BUS27

IO BUS28

IO BUS29

IO BUS30

IO BUS31

IO BUS32

IO BUS33

IO BUS34

IO BUS35

IO BUS36

IO BUS37

IO BUS38

IO BUS39

IO BUS40

IO BUS41

IO BUS42

IO BUS43

IO37

DM2 AIN0 IO42 IO43

PWREN# AIN6

AIN3

NC AIN5 IO41

IO34 RXD TXD IO36

AIN4 IO39

AIN7 IO38

AIN2 AIN1 CS# IO35

3V3

R5 27

R15 10K

9

10 RESET PROG R4 27

36 USB2DP DP2

FB1

R3 27

34 USB1DM DM1

GND CORE GND PLL TEST GND IO GND CORE GND CORE

6

8

30

35

53

3

7 1.8V VCC PLL IN

1.8V VREG OUT

1

R2 27

5 33

XTOUT USB1DP DP1

C12 100nF Y1

4 XTIN

+ C10

4.7uF C11 100nF

12MHz C13 27pF C14 27pF

September 2011 69

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