DESIGN CYCLE
kHz increment value. This
increment value resulted in an
NCO output frequency of
1.997 kHz:
■ SCREENSHOT 6. 1.00488 kHz
with a duty cycle of 49.99% ain't
too shabby.
NCO1INCH = 0x01;
NCO1INCL = 0x06;
Loading the NCO increment
register with 0x0107 produced
2.005 kHz. In either case, the
duty cycle varied between 49.99
and 50.02%.
Thus far, we’ve been
navigating in the upper half of
Figure 1, which is a block
diagram of the PIC16(L)F1507’s
NCO module. Let’s flip that
N1PFM bit and check out the NCO in Pulse Frequency (PF)
mode. If you take another look at Figure 1, you will notice
that PF mode uses the NCO’s SR Latch instead of the D flip-flop. The best way to understand how the NCO works in PF
mode is to create a square wave. Let’s forget about the SR
Latch for now and concentrate on the Ripple Counter. The
Ripple Counter’s time until overflow is determined by the
value loaded into the N1PWS bits and the NCO clock
frequency. In our case, the NCO clock is running at 16
equates to 62 nS. If we set the Ripple Counter to overflow
every 128 clock cycles, it will overflow in 8 µS with a 16
MHz clock input.
Note that the Ripple Counter can only count when the
SR Latch is set. The SR Latch gets a set pulse with every
overflow of the NCO accumulator. The accumulator overflow
pulse is derived from logically ANDing the most significant bit
of the 20-bit accumulator and the NCO clock. The accumulator
overflow sets the SR Latch and forces the SR Latch Q
output logically high. With Q logically high, the NCO clock
■ FIGURE 1. If you're into
working with counters, latches,
flip-flops, and clocks, the NCO
will keep you busy for days.
February 2012 57